3D semiconductor devices and structures with at least two single-crystal layers
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second transistors each include at least two side-gates, and where through the first metal layers power is provided to at least one of the second transistors.
1. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising first transistors,
wherein said first transistors each comprises a single crystal channel;
first metal layers interconnecting at least said first transistors; and
a second level comprising a second single crystal layer, said second level comprising second transistors,
wherein a top surface of said first level comprises a first oxide region and a bottom surface of said second level comprises a second oxide region,
wherein said second level overlays said first level,
wherein said second level is bonded to said first level,
wherein said bonded comprises oxide to oxide bonds,
wherein said second transistors each comprises at least two side-gates, and
wherein through said first metal layers power is provided to at least one of said second transistors.
2. The device according to claim 1 ,
wherein a top surface of said first level comprises a first metal region and a bottom surface of said second level comprises a second metal region, and
wherein said bonded comprises metal to metal bonds.
3. The device according to claim 1 ,
wherein at least one of said first transistors controls power delivery to at least one of said second transistors.
4. The device according to claim 1 ,
wherein said first level comprises third transistors and fourth transistors,
wherein said fourth transistors are overlying said third transistors, and
wherein said third transistors and said fourth transistors are self-aligned, being processed following the same lithography step.
5. The device according to claim 1 ,
wherein at least one of said second transistors comprises hafnium oxide.
6. The device according to claim 1 ,
wherein said first level comprises a memory array, and
wherein said second level comprises control circuits for said memory array.
7. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising first transistors,
wherein said first transistors each comprises a single crystal channel;
first metal layers interconnecting at least said first transistors; and
a second level comprising a second single crystal layer, said second level comprising second transistors,
wherein a top surface of said first level comprises a first oxide region and a bottom surface of said second level comprises a second oxide region,
wherein said second level overlays said first level,
wherein said second level is bonded to said first level,
wherein said bonded comprises oxide to oxide bonds,
wherein at least one of said second transistors comprises hafnium oxide, and
wherein at least one of said second transistors is capable of driving a signal to an external device.
8. The device according to claim 7 ,
wherein said first level comprises third transistors and fourth transistors,
wherein said fourth transistors are overlying said third transistors, and
wherein said third transistors and said fourth transistors are self-aligned,
being processed following the same lithography step.
9. The device according to claim 7 ,
wherein a top surface of said first level comprises a first metal region and a bottom surface of said second level comprises a second metal region, and
wherein said bonded comprises metal to metal bonds.
10. The device according to claim 7 ,
wherein at least one of said first transistors is capable of operating at a maximum operating first voltage,
wherein at least one of said second transistors is capable of operating at a maximum operating second voltage, and
wherein said maximum operating second voltage is greater than said maximum operating first voltage.
11. The device according to claim 7 ,
wherein each of said second transistors are horizontally oriented, and
wherein each of said second transistors comprise at least two side gates.
12. The device according to claim 7 ,
wherein said device comprises an array of memory cells,
wherein a plurality of said memory cells comprise at least two of said second transistors, and
wherein said first level comprises a periphery circuit to control said array of memory cells.
13. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising first transistors,
wherein said first transistors each comprises a single crystal channel;
first metal layers interconnecting at least said first transistors; and
a second level comprising a second single crystal layer, said second level comprising second transistors,
wherein a top surface of said first level comprises a first oxide region and a first metal region,
wherein a bottom surface of said second level comprises a second oxide region and a second metal region,
wherein said second level overlays said first level,
wherein said second level is bonded to said first level,
wherein said bonded comprises oxide to oxide bonds,
wherein said bonded comprises metal to metal bonds, and
wherein at least one of said first metal layers is part of the power delivery path to at least one of said second transistors.
14. The device according to claim 13 ,
wherein at least one of said first transistors is capable of operating at a maximum operating first voltage,
wherein at least one of said second transistors is capable of operating at a maximum operating second voltage, and
wherein said maximum operating second voltage is greater than said maximum operating first voltage.
15. The device according to claim 13 ,
wherein each of said second transistors are horizontally oriented, and
wherein each of said second transistors comprise at least two side gates.
16. The device according to claim 13 ,
wherein said device comprises an array of memory cells,
wherein a plurality of said memory cells comprise at least two of said second transistors, and
wherein said first level comprises a periphery circuit to control said array of memory cells.
17. The device according to claim 13 ,
wherein at least one of said second transistors comprises hafnium oxide.