Hierarchical cyclic redundancy check techniques

1. A method for wireless communication, comprising:

appending, during a first encoding stage, a first set of cyclic redundancy check bits having a first size to each code block of a plurality of code blocks;

concatenating two or more code blocks from the plurality of code blocks into a first set of code blocks, each code block of the two or more code blocks including the appended first set of cyclic redundancy check bits;

appending, during a second encoding stage, a second set of cyclic redundancy check bits having a second size to the first set of code blocks; and

transmitting a message comprising the plurality of code blocks including the appended first set of cyclic redundancy check bits and the appended second set of cyclic redundancy check bits.

2. The method of claim 1 , further comprising:

distributing the second set of cyclic redundancy check bits to each code block of the two or more code blocks, wherein a first code block of the two or more code blocks is appended with a first portion of the second set of cyclic redundancy check bits and a second code block of the two or more code blocks is appended with a second portion of the second set of cyclic redundancy check bits.

3. The method of claim 1 , further comprising:

concatenating the first set of code blocks and a second set of code blocks into a third set of code blocks, the second set of code blocks comprising two or more additional code blocks from the plurality of code blocks that each includes the appended first set of cyclic redundancy check bits, wherein the second set of code blocks is appended with the second set of cyclic redundancy check bits; and

appending, during a third encoding stage, a third set of cyclic redundancy check bits having a third size to the concatenated first set of code blocks and second set of code blocks, wherein the message comprises the plurality of code blocks including the appended first set of cyclic redundancy check bits, the appended second set of cyclic redundancy check bits, and the appended third set of cyclic redundancy check bits.

4. The method of claim 3 , further comprising:

distributing the third set of cyclic redundancy check bits to the first set of code blocks and the second set of code blocks, wherein the first set of code blocks is appended with a first portion of the third set of cyclic redundancy check bits and the second set of code blocks is appended with a second portion of the third set of cyclic redundancy check bits.

5. The method of claim 1 , further comprising:

transmitting a second message indicating a cyclic redundancy check configuration, wherein appending the first set of cyclic redundancy check bits, concatenating the two or more code blocks, and appending the second set of cyclic redundancy check bits is based at least in part on the cyclic redundancy check configuration.

6. The method of claim 5 , wherein the second message is transmitted via medium access control (MAC)-control element signaling, downlink control information, radio resource control signaling, or any combination thereof.

7. The method of claim 1 , wherein the first encoding stage and the second encoding stage are from a plurality of encoding stages for encoding the message, each encoding stage of the plurality of encoding stages being associated with appending respective sets of cyclic redundancy check bits to one or more code blocks of the plurality of code blocks.

8. The method of claim 1 , further comprising:

determining a set of cyclic redundancy check bits corresponding to respective encoding stages and one or more polynomial functions associated with the set of cyclic redundancy check bits; and

determining a number of the plurality of code blocks corresponding to the respective encoding stages, wherein appending the first set of cyclic redundancy check bits, concatenating the two or more code blocks, and appending the second set of cyclic redundancy check bits is based at least in part on the set of cyclic redundancy check bits, the one or more polynomial functions, the number of the plurality of code blocks, and the respective encoding stages.

9. The method of claim 1 , further comprising:

receiving a feedback message in response to the transmitted message; and

retransmitting one or more code blocks from the plurality of code blocks based at least in part on the feedback message indicating a decoding failure associated with the one or more code blocks including the appended first set of cyclic redundancy check bits having the first size or a decoding failure associated with the first set of code blocks including the appended second set of cyclic redundancy check bits having the second size.

10. The method of claim 9 , wherein retransmitting the one or more code blocks from the plurality of code blocks comprises:

retransmitting a single code block based at least in part on the feedback message indicating the decoding failure associated with the one or more code blocks including the appended first set of cyclic redundancy check bits having the first size.

11. The method of claim 9 , wherein retransmitting the one or more code blocks from the plurality of code blocks comprises:

retransmitting the first set of code blocks based at least in part on the feedback message indicating the decoding failure associated with the first set of code blocks including the appended second set of cyclic redundancy check bits having the second size.

12. The method of claim 1 , further comprising:

selecting a cyclic redundancy check encoding scheme from a plurality of cyclic redundancy check encoding schemes, wherein appending the first set of cyclic redundancy check bits, concatenating the two or more code blocks, and appending the second set of cyclic redundancy check bits is based at least in part on the cyclic redundancy check encoding scheme.

13. The method of claim 12 , wherein the cyclic redundancy check encoding scheme indicates whether the second set of cyclic redundancy check bits are appended to a last code block of the first set of code blocks or distributed to each code block of the first set of code blocks.

14. The method of claim 12 , wherein the cyclic redundancy check encoding scheme is selected from a preconfigured list of cyclic redundancy check encoding schemes.

15. The method of claim 12 , wherein the cyclic redundancy check encoding scheme is semi-statically selected based at least in part on a channel type for transmitting the message, a size of respective code blocks from the plurality of code blocks, or a size of code block groups, or any combination thereof.

16. The method of claim 12 , wherein the cyclic redundancy check encoding scheme is dynamically selected based at least in part on an error probability associated with transmitting the message.

17. The method of claim 1 , wherein a total number of cyclic redundancy check bits of the message comprises a sum of the first set of cyclic redundancy check bits and the second set of cyclic redundancy check bits.

18. The method of claim 1 , wherein the second set of cyclic redundancy check bits are appended to a temporally last code block of the first set of code blocks based at least in part on concatenating the two or more code blocks.

19. A method for wireless communication, comprising:

receiving a message comprising a plurality of code blocks, wherein each code block of the plurality of code blocks is appended with a first set of cyclic redundancy check bits having a first size, and wherein two or more concatenated code blocks of the plurality of code blocks are appended with a second set of cyclic redundancy check bits having a second size; and

attempting to decode the plurality of code blocks based at least in part on receiving the message.

20. The method of claim 19 , further comprising:

transmitting a feedback message indicating a decoding failure for one or more code blocks including the appended first set of cyclic redundancy check bits, or a decoding failure for a first set of code blocks including the appended second set of cyclic redundancy check bits, or any combination thereof.

21. The method of claim 20 , further comprising:

receiving a retransmission of a single code block based at least in part on the feedback message indicating the decoding failure associated with the one or more code blocks including the appended first set of cyclic redundancy check bits.

22. The method of claim 20 , further comprising:

receiving a retransmission of the first set of code blocks based at least in part on the feedback message indicating the decoding failure associated with the first set of code blocks including the appended second set of cyclic redundancy check bits.

23. The method of claim 19 , further comprising:

receiving a second message indicating a cyclic redundancy check configuration, wherein the message includes the plurality of code blocks having the appended first set of cyclic redundancy check bits and the two or more concatenated code blocks having the appended second set of cyclic redundancy check bits based at least in part on the cyclic redundancy check configuration.

24. The method of claim 23 , wherein the second message is received via medium access control (MAC)-control element signaling, downlink control information, radio resource control signaling, or any combination thereof.

25. The method of claim 19 , wherein a first code block of the two or more concatenated code blocks is appended with a first portion of the second set of cyclic redundancy check bits and a second code block of the two or more concatenated code blocks is appended with a second portion of the second set of cyclic redundancy check bits.

26. The method of claim 19 , wherein the message comprises a third set of cyclic redundancy check bits appended to a concatenation of a first set of code blocks and a second set of code blocks, the first set of code blocks comprising the two or more concatenated code blocks with the second set of cyclic redundancy check bits appended to the first set of code blocks, and the second set of code blocks comprising two or more additional concatenated code blocks with the second set of cyclic redundancy check bits appended to the second set of code blocks, and wherein decoding the message is based at least in part on the third set of cyclic redundancy check bits appended to the concatenation of the first set of code blocks and the second set of code blocks.

27. The method of claim 19 , wherein a total number of cyclic redundancy check bits of the message comprises a sum of the first set of cyclic redundancy check bits and the second set of cyclic redundancy check bits.

28. An apparatus for wireless communication, comprising:

a processor;

a memory coupled with the processor; and

instructions stored in the memory and executable by the processor to cause the apparatus to:

append, during a first encoding stage, a first set of cyclic redundancy check bits having a first size to each code block of a plurality of code blocks;

concatenate two or more code blocks from the plurality of code blocks into a first set of code blocks, each code block of the two or more code blocks including the appended first set of cyclic redundancy check bits;

append, during a second encoding stage, a second set of cyclic redundancy check bits having a second size to the first set of code blocks; and

transmit a message comprising the plurality of code blocks including the appended first set of cyclic redundancy check bits and the appended second set of cyclic redundancy check bits.

29. The apparatus of claim 28 , wherein the instructions are further executable by the processor to cause the apparatus to:

distribute the second set of cyclic redundancy check bits to each code block of the two or more code blocks, wherein a first code block of the two or more code blocks is appended with a first portion of the second set of cyclic redundancy check bits and a second code block of the two or more code blocks is appended with a second portion of the second set of cyclic redundancy check bits.

30. An apparatus for wireless communication, comprising:

a processor;

a memory coupled with the processor; and

instructions stored in the memory and executable by the processor to cause the apparatus to:

receive a message comprising a plurality of code blocks, wherein each code block of the plurality of code blocks is appended with a first set of cyclic redundancy check bits having a first size, and wherein two or more concatenated code blocks of the plurality of code blocks are appended with a second set of cyclic redundancy check bits having a second size; and

attempt to decode the plurality of code blocks based at least in part on receiving the message.