IP Library › Granted Patent US 11,804,544
Granted Patent B2
US 11,804,544 · App. 17/575,655 · Granted Oct 31, 2023

High electron mobility transistor and method for fabricating the same

Inventors: Shin-Chuan Huang (Tainan, TW); Chih-Tung Yeh (Taoyuan, TW); Chun-Ming Chang (Kaohsiung, TW); Bo-Rong Chen (Hsinchu County, TW); Wen-Jung Liao (Hsinchu, TW); Chun-Liang Hou (Hsinchu County, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/7786H01L21/26546H01L29/2003H01L29/205H01L29/207H01L29/66462H01L21/2654H01L21/28264H01L29/41766H01L29/4236
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Quick Facts
Patent No.
US 11,804,544
App. No.
17/575,655
Granted
Oct 31, 2023
Kind
B2
Abstract

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

Claims (26)

1. A method for fabricating high electron mobility transistor (HEMT), comprising:

forming a buffer layer on a substrate;

forming a barrier layer on the buffer layer;

forming a hard mask on the barrier layer;

performing an ion implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer;

removing the hard mask, the doped region, and the barrier layer to form a first trench, wherein a thickness of the doped region in the barrier layer is less than a thickness of the doped region in the buffer layer;

forming a gate dielectric layer on the hard mask and into the first trench; and

forming a gate electrode on the gate dielectric layer.

2. The method of claim 1 , further comprising:

forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

3. The method of claim 2 , further comprising:

removing the gate dielectric layer, the hard mask, and the barrier layer to form a second trench and a third trench adjacent to two sides of the gate electrode; and

forming the source electrode in the second trench and the drain electrode in the third trench.

4. The method of claim 1 , wherein the buffer layer comprises a group III-V semiconductor.

5. The method of claim 4 , wherein the buffer layer comprises gallium nitride (GaN).

6. The method of claim 1 , wherein the barrier layer comprises Al x Ga 1-x N.

7. The method of claim 1 , wherein the doped region comprises fluorine.

8. The method of claim 7 , wherein a concentration of fluorine decreases from the barrier layer to the buffer layer.

9. A method for fabricating high electron mobility transistor (HEMT), comprising:

forming a buffer layer on a substrate;

forming a barrier layer on the buffer layer;

forming a hard mask on the barrier layer;

performing an ion implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer;

removing the hard mask, the doped region, and the barrier layer to form a first trench, wherein a bottom surface of the first trench is even with a bottom surface of the barrier layer;

forming a gate dielectric layer on the hard mask and into the first trench; and

forming a gate electrode on the gate dielectric layer.

Priority Claims (1)
TW 108124137 · Jul 9, 2019 · national
Continuity (2)
Division 16533812 · Aug 7, 2019
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