IP Library Granted Patent US 11,929,347
Granted Patent B2
US 11,929,347 · App. 17/579,259 · Granted Mar 12, 2024

Mixed exposure for large die

Inventors: Javier A. Delacruz (San Jose, CA); Belgacem Haba (Saratoga, CA)
Assignee: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
H01L24/97H01L21/682H01L23/5384H01L23/5389H01L25/0655H01L2225/06541
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Quick Facts
Patent No.
US 11,929,347
App. No.
17/579,259
Granted
Mar 12, 2024
Kind
B2
Abstract

Techniques and arrangements for performing exposure operations on a wafer utilizing both a stepper apparatus and an aligner apparatus. The exposure operations are performed with respect to large composite base dies, e.g., interposers, defined within the wafer, where the interposers will become a part of microelectronic devices by coupling with active dies or microchips. The composite base dies may be coupled to the active dies via “native interconnects” utilizing direct bonding techniques. The stepper apparatus may be used to perform exposure operations on active regions of the composite base dies to provide a fine pitch for the native interconnects, while the aligner apparatus may be used to perform exposure operations on inactive regions of the composite base dies to provide a coarse pitch for interfaces with passive regions of the composite base dies.

Claims (74)

1. A method of manufacturing two or more base dies on a single wafer comprising:

exposing a first region of a first base die using a first photolithographic-exposure apparatus;

subsequent to exposing the first region of the first base die, exposing a first region of a second base die using the first photolithographic-exposure apparatus;

exposing a second region of the first base die using a second photolithographic-exposure apparatus; and

exposing a second region of the second base die using the second photolithographic-exposure apparatus,

wherein the first photolithographic-exposure apparatus is configured to resolve smaller features with respect to features resolved by the second photolithographic-exposure apparatus.

2. The method of claim 1 , wherein:

a size of the first region of the first base die is substantially equal to a size of the first region of the second base die; and

the size of the first region of the first base die and the size of the first region of the second base die are both smaller than a size of the first base die and a size of the second base die.

3. The method of claim 1 , wherein the first region of the first base die and the first region of the second base die are non-contiguous.

4. The method of claim 1 , wherein an area of the first base die consists only of (i) the first region of the first base die and (ii) the second region of the first base die.

5. The method of claim 1 , wherein the first region of the first base die is disposed substantially at a center of the first base die.

6. The method of claim 1 , wherein (i) exposing the first region of the first base die and (ii) exposing the first region of the second base die are performed using a same photoresist layer.

7. The method of claim 1 , wherein (i) exposing the first region of the first base die and (ii) exposing the first region of the second base die are performed using different photoresist layers.

8. The method of claim 1 , further comprising:

etching the single wafer between use of the first photolithographic-exposure apparatus and use of the second photolithographic-exposure apparatus.

9. The method of claim 1 , further comprising:

bonding a first integrated circuit to a first portion of the first region of the first base die; and

bonding a second integrated circuit to a second portion of the first region of the first base die.

10. The method of claim 9 , wherein:

bonding the first integrated circuit to the first portion of the first region of the first base die comprises hybrid bonding; and

bonding the second integrated circuit to the second portion of the first region of the first base die comprises hybrid bonding.

11. The method of claim 10 , wherein;

a pitch of native interconnects in (i) the first region of the first base die and (ii) the first region of the second base die is in a range of one to 10 microns; and

a pitch of native interconnects in (i) the second region of the first base die and (ii) the second region of the second base die is 100 microns or more.

12. The method of claim 1 , wherein:

(i) exposing the second region of the first base die and (ii) exposing the second region of the second base die exposes metal fill for backend of line (BEOL) layers of the first base die and the second base die; and

the method further comprises:

exposing the second region of the first base die using the second photolithographic-exposure apparatus a second time to expose through silicon vias (TSVs) in the second region of the first base die; and

exposing the second region of the second base die using the second photolithographic-exposure apparatus a second time to expose through TSVs in the second region of the second base die.

13. The method of claim 1 , wherein the first photolithographic-exposure apparatus is a stepper apparatus.

14. The method of claim 1 , wherein the second photolithographic-exposure apparatus is an aligner apparatus.

15. The method of claim 1 , wherein the first region of the first base die comprises an active region.

16. The method of claim 1 , wherein the second region of the first base die comprises an inactive region.

17. The method of claim 1 , wherein:

the first photolithographic-exposure apparatus performs exposing the first region of the first base die;

then the second photolithographic-exposure apparatus performs exposing the second region of the first base die;

then the first photolithographic-exposure apparatus performs exposing the first region of the second base die using the first photolithographic-exposure apparatus; and

then the second photolithographic-exposure apparatus performs exposing the second region of the second base die.

18. The method of claim 1 , wherein:

the first photolithographic-exposure apparatus performs exposing the first region of the first base die;

then the first photolithographic-exposure apparatus performs exposing the first region of the second base die using the first photolithographic-exposure apparatus;

then the second photolithographic-exposure apparatus performs exposing the second region of the first base die; and

then the second photolithographic-exposure apparatus performs exposing the second region of the second base die.

19. An arrangement comprising:

a first photolithographic-exposure apparatus; and

a second photolithographic-exposure apparatus,

wherein the arrangement is configured to perform actions comprising:

exposing a first region of a first base die using the first photolithographic-exposure apparatus;

subsequent to exposing the first region of the first base die, exposing a first region of a second base die using the first photolithographic-exposure apparatus;

exposing a second region of the first base die using the second photolithographic-exposure apparatus; and

exposing a second region of the second base die using the second photolithographic-exposure apparatus,

wherein the first photolithographic-exposure apparatus is configured to resolve smaller features with respect to features resolved by the second photolithographic-exposure apparatus.

20. The arrangement of claim 19 , wherein (i) exposing the first region of the first base die and (ii) exposing the first region of the second base die are performed using a same photoresist layer.

21. The arrangement of claim 19 , wherein (i) exposing the first region of the first base die and (ii) exposing the first region of the second base die are performed using different photoresist layers.

22. The arrangement of claim 19 , wherein:

(i) exposing the second region of the first base die and (ii) exposing the second region of the second base die exposes metal fill for backend of line (BEOL) layers of the first base die and the second base die; and

the actions further comprise:

exposing the second region of the first base die using the second photolithographic-exposure apparatus a second time to expose through silicon vias (TSVs) in the second region of the first base die; and

exposing the second region of the second base die using the second photolithographic-exposure apparatus a second time to expose through TSVs in the second region of the second base die.

23. The arrangement of claim 19 , wherein the first photolithographic-exposure apparatus is a stepper apparatus.

24. The arrangement of claim 19 , wherein the second photolithographic-exposure apparatus is an aligner apparatus.

25. The arrangement of claim 19 , wherein the first region of the first base die comprises an active region.

26. The arrangement of claim 19 , wherein the second region of the first base die comprises an inactive region.

27. The arrangement of claim 19 , wherein:

the first photolithographic-exposure apparatus performs exposing the first region of the first base die;

then the second photolithographic-exposure apparatus performs exposing the second region of the first base die;

then the first photolithographic-exposure apparatus performs exposing the first region of the second base die using the first photolithographic-exposure apparatus; and

then the second photolithographic-exposure apparatus performs exposing the second region of the second base die.

28. The arrangement of claim 19 , wherein:

the first photolithographic-exposure apparatus performs exposing the first region of the first base die;

then the first photolithographic-exposure apparatus performs exposing the first region of the second base die using the first photolithographic-exposure apparatus;

then the second photolithographic-exposure apparatus performs exposing the second region of the first base die; and

then the second photolithographic-exposure apparatus performs exposing the second region of the second base die.

Assignments (4)
CHANGE OF NAME Recorded Jul 6, 2023
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 064224/0958 →
SECURITY INTEREST Recorded May 3, 2023
From: ADEIA GUIDES INC.; ADEIA IMAGING LLC; ADEIA MEDIA HOLDINGS LLC; ADEIA MEDIA SOLUTIONS INC.; ADEIA SEMICONDUCTOR ADVANCED TECHNOLOGIES INC.; ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.; ADEIA SEMICONDUCTOR INC.; ADEIA SEMICONDUCTOR SOLUTIONS LLC; ADEIA SEMICONDUCTOR TECHNOLOGIES LLC; ADEIA SOLUTIONS LLC
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 063529/0272 →
CHANGE OF NAME Recorded Aug 30, 2022
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 061357/0485 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2022
From: DELACRUZ, JAVIER A.; HABA, BELGACEM
To: INVENSAS CORPORATION
Reel/Frame 059285/0549 →
Cited By (1)
US 12,381,173