Granted Patent B2

US 12,300,313 · App. 17/580,862 · Granted May 13, 2025

Inventors: Farnood Merrikh Bayat (Goleta, CA); Xinjie Guo (Goleta, CA); Dmitri Strukov (Goleta, CA); Nhan Do (Saratoga, CA); Hieu Van Tran (San Jose, CA); Vipin Tiwari (Dublin, CA); Mark Reiten (Alamo, CA)

Assignees: Silicon Storage Technology, Inc.; The Regents of the University of California

G11C11/54G06F3/061G06F3/0655G06F3/0688G06N3/04G06N3/045G06N3/063G11C16/08G11C16/12G11C16/16G11C16/3436G11C29/38

Abstract

Claims (56)

1. A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:

a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs, a second non-floating gate disposed over and insulated from the source region, and a third non-floating gate disposed over and insulated from the floating gate;

each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;

the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;

a first plurality of neurons configured to receive the first plurality of outputs;

wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:

a plurality of first lines each electrically connecting together the first non-floating gates in one of the rows of the memory cells and physically isolated from the first non-floating gates in other rows of the memory cells;

a plurality of second lines each electrically connecting together the second non-floating gates in one of the columns of the memory cells and physically isolated from the second non-floating gates in other columns of the memory cells;

a plurality of third lines each electrically connecting together the third non-floating gates in one of the rows of the memory cells and physically isolated from the third non-floating gates in other rows of the memory cells;

a plurality of fourth lines each electrically connecting together the source regions in one of the rows of the memory cells and physically isolated from the source regions in other rows of the memory cells;

a plurality of fifth lines each electrically connecting together the drain regions in one of the columns of the memory cells and physically isolated from the drain regions in other columns of the memory cells;

wherein the first plurality of synapses is configured to receive the first plurality of inputs on the plurality of first lines, and to provide the first plurality of outputs on the plurality of fifth lines.

2. The neural network device of claim 1 , wherein for each of the plurality of fifth lines, one of the first plurality of outputs is provided thereon which is a sum of currents through the memory cells multiplied by respective weight values stored in the memory cells, for all of the memory cells in the one column of the memory cells.

3. The neural network device of claim 1 , further comprising:

circuitry for logarithmically converting current of the first plurality of inputs to voltage before the receiving of the first plurality of inputs on the plurality of first lines.

4. A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:

a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs, a second non-floating gate disposed over and insulated from the source region, and a third non-floating gate disposed over and insulated from the floating gate;

each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;

the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;

a first plurality of neurons configured to receive the first plurality of outputs;

wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:

a plurality of first lines each electrically connecting together the first non-floating gates in one of the rows of the memory cells and physically isolated from the first non-floating gates in other rows of the memory cells;

a plurality of second lines each electrically connecting together the second non-floating gates in one of the rows of the memory cells and physically isolated from the second non-floating gates in other rows of the memory cells;

a plurality of third lines each electrically connecting together the third non-floating gates in one of the rows of the memory cells and physically isolated from the third non-floating gates in other rows of the memory cells;

a plurality of fourth lines each electrically connecting together the source regions in one of the columns of the memory cells and physically isolated from the source regions in other columns of the memory cells;

a plurality of fifth lines each electrically connecting together the drain regions in one of the columns of the memory cells and physically isolated from the drain regions in other columns of the memory cells;

wherein the first plurality of synapses is configured to receive the first plurality of inputs on the plurality of first lines, and to provide the first plurality of outputs on the plurality of fifth lines.

5. The neural network device of claim 4 , wherein for each of the plurality of fifth lines, one of the first plurality of outputs is provided thereon which is a sum of currents through the memory cells multiplied by respective weight values stored in the memory cells, for all of the memory cells in the one column of the memory cells.

6. A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:

a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs, a second non-floating gate disposed over and insulated from the source region, and a third non-floating gate disposed over and insulated from the floating gate;

each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;

the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;

a first plurality of neurons configured to receive the first plurality of outputs;

wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:

a plurality of first lines each electrically connecting together the first non-floating gates in one of the rows of the memory cells and physically isolated from the first non-floating gates in other rows of the memory cells;

a plurality of second lines each electrically connecting together the second non-floating gates in one of the rows of the memory cells and physically isolated from the second non-floating gates in other rows of the memory cells;

a plurality of third lines each electrically connecting together the third non-floating gates in one of the rows of the memory cells and physically isolated from the third non-floating gates in other rows of the memory cells;

a plurality of fourth lines each electrically connecting together the source regions in one of the columns of the memory cells and physically isolated from the source regions in other columns of the memory cells;

a plurality of fifth lines each electrically connecting together the drain regions in one of the columns of the memory cells and physically isolated from the drain regions in other columns of the memory cells;

wherein the first plurality of synapses is configured to receive the first plurality of inputs on the plurality of first lines, and to provide the first plurality of outputs on the plurality of fourth lines.

7. The neural network device of claim 6 , wherein for each of the plurality of fourth lines, one of the first plurality of outputs is provided thereon which is a sum of currents through the memory cells multiplied by respective weight values stored in the memory cells, for all of the memory cells in the one column of the memory cells.

8. A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:

a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs;

each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;

the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;

a first plurality of neurons configured to receive the first plurality of outputs;

wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:

a plurality of first lines each electrically connecting together the first non-floating gates in one of the rows of the memory cells and physically isolated from the first non-floating gates in other rows of the memory cells;

a plurality of second lines each electrically connecting together the source regions in one of the columns of the memory cells and physically isolated from the source regions in other columns of the memory cells;

a plurality of third lines each electrically connecting together the drain regions in one of the columns of the memory cells and physically isolated from the drain regions in other columns of the memory cells;

wherein the first plurality of synapses is configured to receive the first plurality of inputs on the plurality of first lines, and to provide the first plurality of outputs on the plurality of third lines.

9. The neural network device of claim 8 , wherein for each of the plurality of third lines, one of the first plurality of outputs is provided thereon which is a sum of currents through the memory cells multiplied by respective weight values stored in the memory cells, for all of the memory cells in the one column of the memory cells.

Assignments (1)

Continuity (3)

References Cited (153)