Level verification and adjustment for multi-level cell (MLC) non-volatile memory (NVM)
Non-Volatile Memory (NVM) cells are connected in inverter configurations. The NVM inverter's Voltage Transfer Characteristics (VTC) is used to verify and adjust threshold voltage levels of a Multi-Level Cell (MLC) in an NVM. In one embodiment, the NVM cell is fast programmed to a specific threshold voltage level. The cell threshold level is then verified by applying a gate voltage corresponding to the selected threshold voltage to the NVM inverter. The output voltage of the NVM inverter in response to the applied level gate voltage is detected. When the output voltage of the NVM inverter is out of a predefined output voltage window for the selected threshold voltage level, a fine-tuning programming sequence is applied to the NVM cell until the threshold voltage of the NVM cell is inside the correspondent threshold voltage window. This verification and adjustment scheme for a MLC NVM allows the threshold voltage of the multi-level NVM cells for any specific level to be controlled to a desired accuracy.
1. Structure comprising:
a multi-level cell for use in a nonvolatile memory, said cell including a transistor for storing charge representing any one of 2 n possible values, where n is a selected integer, said transistor comprising a drain, a source and a control gate;
a load device connected in series with said transistor; and
an output terminal connected between said transistor and said load device such that the output voltage on said output terminal assumes approximately the same value when the gate voltage on said transistor is sufficient to turn on said transistor, regardless of the charge stored on said transistor.
2. Structure as in claim 1 wherein said load device comprises a resistor.
3. Structure as in claim 1 wherein said load device comprises an N-type saturated MOS transistor.
4. Structure as in claim 1 wherein said load device comprises a P-type saturation MOS transistor.
5. Structure as in claim 1 , wherein said load device comprises an N-type depletion MOS FET.
6. Structure as in claim 1 , wherein said load device comprises a P-type depletion MOS FET.
7. Structure as in claim 1 , wherein said transistor comprises an N-channel MOS FET and said load device comprises a device with an impedance, said load device being connected between the drain of said N channel MOS FET and a source of a supply voltage.
8. Structure as in claim 7 , wherein said load device comprises a resistor.
9. Structure as in claim 7 , wherein said load device comprises a saturated N-channel MOS transistor.
10. Structure as in claim 7 , wherein said load device comprises a P-type saturated MOS FET.
11. Structure as in claim 7 , wherein said load device comprises an N-type depletion MOS FET.
12. Structure as in claim 7 , wherein said load device comprises a P-type depletion MOS FET.
13. Structure as in claim 7 , wherein the source of said N-channel MOS FET device is connected to system ground.
14. Structure as in claim 1 , wherein said transistor comprises a P-channel MOS FET, and said load device comprises a device with an impedance, said load device being connected between the drain of said P-channel MOS FET and the system ground.
15. Structure as in claim 14 , wherein said load device comprises a resistor.
16. Structure as in claim 14 , wherein said load device comprises a P-type saturated MOS transistor.
17. Structure as in claim 14 , wherein said load device comprises an N-type saturated MOS transistor.
18. Structure as in claim 14 , wherein said load device comprises an N-type depletion MOS FET.
19. Structure as in claim 14 , wherein said load device comprises a P-type depletion MOS FET.
20. Structure as in claim 14 , wherein the source of said P-channel MOS FET device is connected to a source of supply voltage.