Flash memory array with individual memory cell read, program and erase

Inventors: Xinjie Guo (Goleta, CA); Farnood Merrikh Bayat (Goleta, CA); Dmitri Strukov (Goleta, CA); Nhan Do (Saratoga, CA); Hieu Van Tran (San Jose, CA); Vipin Tiwari (Dublin, CA)

Assignee: Silicon Storage Technology, Inc.

G11C16/3431 G11C7/18 G11C8/14 G11C16/0483 G11C16/10 G11C16/14 G11C16/26 G11C16/3427 H01L27/11521 H01L27/11524 H01L27/11558 H01L29/7881

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Quick Facts

Patent No.: US 10,249,375
App. No.: 15/987,735
Granted: Apr 2, 2019
Kind: B2

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Abstract

A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Claims (41)

1. A memory device, comprising:

a substrate of semiconductor material;

a plurality of memory cells formed on the substrate and arranged in an array of rows and columns;

each of the memory cells includes:

spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between,

a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region,

a control gate disposed over and insulated from the floating gate,

a select gate disposed over and insulated from a second portion of the channel region adjacent the drain region, and

an erase gate disposed over and insulated from the source region;

each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells;

each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells;

each of the rows of memory cells includes a control gate line that electrically connects together all the control gates for the row of memory cells;

each of the rows of memory cells includes a select gate line that electrically connects together all the select gates for the row of memory cells; and

each of the columns of memory cells includes an erase gate line that electrically connects together all the erase gates for the column of memory cells and is not electrically connected to erase gates in others of the columns of the memory cells.

2. The memory device of claim 1 , wherein for each of the memory cells, the floating gate extends over and is insulated from a portion of the source region.

3. The memory device of claim 1 , wherein:

the memory cells are arranged in pairs of the memory cells; and

each of the pairs of memory cells shares one of the source regions and one of the source lines.

4. The memory device of claim 3 , wherein each of the pairs of memory cells shares one of the erase gates and one of the erase gate lines.

5. A method of erasing a selected memory cell of a memory device, wherein the memory device comprises:

a substrate of semiconductor material;

a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein one of the plurality of memory cells is a selected memory cell;