Flash memory array with individual memory cell read, program and erase
A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.
1. A memory device, comprising:
a substrate of semiconductor material;
a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein the rows of the memory cells are arranged in alternating even and odd numbered rows;
each of the memory cells includes:
spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region, and
a control gate disposed over and insulated from a second portion of the channel region adjacent the drain region;
each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells;
each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells;
each of the columns of memory cells includes a first control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the odd numbered rows of the memory cells and that is not electrically connected to the control gates of the memory cells in the column of memory cells that are in the even numbered rows of the memory cells; and
each of the columns of memory cells includes a second control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the even numbered rows of the memory cells and that is not electrically connected to the control gates of the memory cells in the column of memory cells that are in the odd numbered rows of the memory cells.
2. The memory device of claim 1 , wherein for each of the memory cells, the floating gate extends over and is insulated from a portion of the source region.
3. The memory device of claim 1 , wherein:
the memory cells are arranged in pairs of the memory cells; and
each of the pairs of memory cells shares one of the source regions and one of the source lines.
4. The memory device of claim 1 , wherein for each of the memory cells, the control gate comprises a first portion laterally adjacent to the floating gate and a second portion that extends up and over the floating gate.
5. A method of erasing a selected memory cell of a memory device, wherein the memory device comprises:
a substrate of semiconductor material;
a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein the rows of the memory cells are arranged in alternating even and odd numbered rows, and wherein one of the plurality of memory cells is a selected memory cell;
each of the memory cells includes:
spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region adjacent the source region, and
a control gate disposed over and insulated from a second portion of the channel region adjacent the drain region;
each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells;
each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells;
each of the columns of memory cells includes a first control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the odd numbered rows of the memory cells and that is not electrically connected to the control gates of the memory cells in the column of memory cells that are in the even numbered rows of the memory cells; and
each of the columns of memory cells includes a second control gate line that electrically connects together all the control gates of the memory cells in the column of memory cells that are in the even numbered rows of the memory cells and that is not electrically connected to the control gates of the memory cells in the column of memory cells that are in the odd numbered rows of the memory cells;
the method comprising:
applying a positive voltage to one of the first or second control gate lines that is electrically connected to the control gate of the selected memory cell, and a ground voltage to all the others of the first and second control gate lines;
applying a ground voltage to one of the source lines that is electrically connected to the source region of the selected memory cell, and a positive voltage to all the others of the source lines; and
applying a ground voltage to all of the bit lines.
6. The method of claim 5 , wherein the positive voltage applied to the one of the first or second control gate lines is greater than the positive voltage applied to the others of the source lines.
7. The method of claim 5 , wherein the positive voltage applied to the one of the first or second control gate lines is at least double than that of the positive voltage applied to the others of the source lines.