Method of scanning an image using non-volatile memory array neural network classifier
A method of scanning N×N pixels using a vector-by-matrix multiplication array by (a) associating a filter of M×M pixels adjacent first vertical and horizontal edges, (b) providing values for the pixels associated with different respective rows of the filter to input lines of different respective N input line groups, (c) shifting the filter horizontally by X pixels, (d) providing values for the pixels associated with different respective rows of the horizontally shifted filter to input lines, of different respective N input line groups, which are shifted by X input lines, (e) repeating steps (c) and (d) until a second vertical edge is reached, (f) shifting the filter horizontally to be adjacent the first vertical edge, and shifting the filter vertically by X pixels, (g) repeating steps (b) through (e) for the vertically shifted filter, and (h) repeating steps (f) and (g) until a second horizontal edge is reached.
1 . A method of scanning a matrix of N×N pixels of an image having N rows of pixels and N columns of pixels using a vector-by-matrix multiplication array that includes rows and columns of non-volatile memory cells configured to store weights, the vector-by-matrix multiplication array configured to receive inputs on input lines that are multiplied by the weights to generate outputs on output lines, the input lines comprise N input line groups each including N of the input lines, the method comprising:
(a) associating a filter with a matrix of M×M pixels of the matrix of N×N pixels adjacent a first vertical edge and a first horizontal edge of the matrix of N×N pixels, where M is less than N;
(b) providing values for the pixels associated with different respective rows of the filter to input lines of different respective N input line groups;
(c) shifting the filter horizontally along the matrix of N×N pixels by X pixels away from the first vertical edge;
(d) providing values for the pixels associated with different respective rows of the horizontally shifted filter to input lines, of different respective N input line groups, which are shifted by X input lines for each of the respective N input line groups;
(e) repeating steps (c) and (d) until a second vertical edge of the matrix of N×N pixels is reached;
(f) shifting the filter horizontally to be adjacent the first vertical edge, and shifting the filter vertically by X pixels away from the first horizontal edge;
(g) repeating steps (b) through (e) for the vertically shifted filter; and
(h) repeating steps (f) and (g) until a second horizontal edge of the matrix of N×N pixels is reached.
2 . The method of claim 1 , wherein X equals 2 and M equals 6.
3 . The method of claim 1 , wherein each of the non-volatile memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a first non-floating gate disposed over and insulated from a second portion of the channel region.
4 . The method of claim 3 , wherein each of the non-volatile memory cells includes a second non-floating gate disposed over and insulated from the source region, and a third non-floating gate disposed over and insulated from the floating gate.
5 . The method of claim 4 , wherein:
each of the input lines electrically connects together the first non-floating gates in one of the rows of the non-volatile memory cells; and
each of the output lines electrically connects together the drain regions in one of the columns of the non-volatile memory cells.
6 . The method of claim 5 , wherein the vector-by-matrix multiplication array comprises:
a plurality of first lines each electrically connecting together the second non-floating gates in one of the columns of the non-volatile memory cells;
a plurality of second lines each electrically connecting together the third non-floating gates in one of the rows of the non-volatile memory cells; and
a plurality of third lines each electrically connecting together the source regions in one of the rows of the non-volatile memory cells.
7 . The method of claim 5 , wherein the vector-by-matrix multiplication array comprises:
a plurality of first lines each electrically connecting together the second non-floating gates in one of the rows of the non-volatile memory cells;
a plurality of second lines each electrically connecting together the third non-floating gates in one of the rows of the non-volatile memory cells; and
a plurality of third lines each electrically connecting together the source regions in one of the columns of the non-volatile memory cells.
8 . The method of claim 4 , wherein:
a first plurality of the input lines each electrically connects together the first non-floating gates of odd row non-volatile memory cells in one of the columns of the non-volatile memory cells;
a second plurality of the input lines each electrically connects together the first non-floating gates of even row non-volatile memory cells in one of the columns of the non-volatile memory cells; and
each of the output lines electrically connects together the source regions in one of the rows of the non-volatile memory cells.
9 . The method of claim 8 , wherein the vector-by-matrix multiplication array comprises:
a plurality of first lines each electrically connecting together the second non-floating gates in one of the columns of the non-volatile memory cells;
a plurality of second lines each electrically connecting together the third non-floating gates in one of the rows of the non-volatile memory cells; and
a plurality of third lines each electrically connecting together the drain regions in one of the columns of the non-volatile memory cells.
10 . The method of claim 8 , wherein the vector-by-matrix multiplication array comprises:
a plurality of first lines each electrically connecting together the second non-floating gates in one of the columns of the non-volatile memory cells;
a plurality of second lines each electrically connecting together the third non-floating gates in one of the rows of the non-volatile memory cells;
a plurality of third lines each electrically connecting together the drain regions of odd row non-volatile memory cells in one of the columns of the non-volatile memory cells; and
a plurality of fourth lines each electrically connecting together the drain regions of even row non-volatile memory cells in one of the columns of the non-volatile memory cells.
11 . The method of claim 8 , wherein the vector-by-matrix multiplication array comprises:
a plurality of first lines each electrically connecting together the second non-floating gates in one of the rows of the non-volatile memory cells;
a plurality of second lines each electrically connecting together the third non-floating gates of odd row non-volatile memory cells in one of the columns of the non-volatile memory cells;
a plurality of third lines each electrically connecting together the third non-floating gates of even row non-volatile memory cells in one of the columns of the non-volatile memory cells;
a plurality of fourth lines each electrically connecting together the drain regions of odd row non-volatile memory cells in one of the columns of the non-volatile memory cells; and
a plurality of fifth lines each electrically connecting together the drain regions of even row non-volatile memory cells in one of the columns of the non-volatile memory cells.
12 . The method of claim 4 , wherein:
each of the input lines electrically connects together the first non-floating gates in one of the rows of the non-volatile memory cells; and
each of the output lines electrically connects together the source regions in one of the columns of the non-volatile memory cells.
13 . The method of claim 12 , wherein the vector-by-matrix multiplication array comprises:
a plurality of first lines each electrically connecting together the second non-floating gates in one of the rows of the non-volatile memory cells;
a plurality of second lines each electrically connecting together the third non-floating gates in one of the rows of the non-volatile memory cells; and
a plurality of third lines each electrically connecting together the drain regions in one of the columns of the non-volatile memory cells.
14 . The method of claim 3 , wherein:
each of the input lines electrically connects together the first non-floating gates in one of the rows of the non-volatile memory cells; and
each of the output lines electrically connects together the drain regions in one of the columns of the non-volatile memory cells.
15 . The method of claim 14 , wherein the vector-by-matrix multiplication array comprises:
a plurality of first lines each electrically connecting together the source regions in one of the columns of the non-volatile memory cells.
16 . The method of claim 3 , wherein:
a first plurality of the input lines each electrically connects together the first non-floating gates of odd row non-volatile memory cells in one of the columns of the non-volatile memory cells;
a second plurality of the input lines each electrically connects together the first non-floating gates of even row non-volatile memory cells in one of the columns of the non-volatile memory cells; and
each of the output lines electrically connects together the source regions in one of the rows of the non-volatile memory cells.
17 . The method of claim 16 , wherein the vector-by-matrix multiplication array comprises:
a plurality of first lines each electrically connecting together the drain regions in one of the columns of the non-volatile memory cells.