Semiconductor structure and method of forming the same
A method of forming a semiconductor structure includes following operations. A memory layer is formed over the first gate electrode. A channel layer is formed over the memory layer. A first SUT treatment is performed. A second dielectric layer is formed over the memory layer and the channel layer. A source electrode and a drain electrode are formed in the second dielectric layer. A temperature of the first SUT treatment is less than approximately 400° C.
1. A method of forming a semiconductor structure, comprising:
forming a first gate electrode in a first dielectric layer;
forming a memory layer over the first gate electrode;
forming a channel layer over the memory layer;
performing a first simultaneous ultraviolet and thermal (SUT) treatment;
forming a second dielectric layer over the memory layer and the channel layer; and
forming a source electrode and a drain electrode in the second dielectric layer, wherein a temperature of the first SUT treatment is less than approximately 400° C.
2. The method of claim 1 , wherein the first SUT treatment is performed on the memory layer prior to the forming of the channel layer.
3. The method of claim 2 , further comprising performing a second SUT treatment on the channel layer after the forming of the channel layer.
4. The method of claim 3 , wherein a temperature of the second SUT treatment and the temperature of the first SUT treatment are the same.
5. The method of claim 1 , wherein first SUT treatment is performed on the memory layer and the channel layer after the forming of the channel layer.
6. The method of claim 1 , wherein the first SUT treatment is performed on the memory layer and the channel layer after the forming of the second dielectric layer.
7. The method of claim 1 , wherein the temperature of the first SUT treatment is between approximately 100° C. and approximately 400° C.
8. The method of claim 1 , wherein a duration of the first SUT treatment is less than approximately 1 hour.
9. The method of claim 1 , further comprising forming a second gate electrode in the second dielectric layer.
10. A method of forming a semiconductor structure, comprising:
forming a gate electrode in a first dielectric layer;
forming a memory layer over the gate electrode;
performing a first simultaneous ultraviolet and thermal (SUT) treatment on the memory layer;
forming a channel layer over the memory layer after the first SUT treatment; and
forming a second dielectric layer over the memory layer and the channel layer,
wherein a temperature of the first SUT treatment is less than approximately 400° C.
11. The method of claim 10 , further comprising performing a second SUT treatment on the channel layer after the forming of the channel layer.
12. The method of claim 11 , wherein a temperature of the second SUT treatment and the temperature of the first SUT treatment are the same.
13. The method of claim 10 , further comprising forming a source electrode and a drain electrode in the second dielectric layer.
14. A method of forming a semiconductor structure, comprising:
forming a first gate electrode in a first dielectric layer; forming a memory layer over the first gate electrode;
forming a channel layer over the memory layer;
performing a simultaneous ultraviolet and thermal (SUT) treatment on the memory layer and the channel layer;
forming a second dielectric layer over the memory layer and the channel layer; and
forming a source electrode and a drain electrode in the second dielectric layer, wherein a temperature of the SUT treatment is less than approximately 400° C.
15. The method of claim 14 , wherein the SUT treatment is performed after the forming of the channel layer.
16. The method of claim 14 , wherein the SUT treatment is performed after the forming of the second dielectric layer.
17. The method of claim 16 , further comprising patterning the memory layer and the channel layer prior to the forming of the second dielectric layer.
18. The method of claim 16 , further comprising forming a second gate electrode in the second dielectric layer.
19. The method of claim 18 , wherein the second gate electrode is separated from the source electrode and the drain electrode by the second dielectric layer.
20. The method of claim 18 , wherein the second gate electrode is separated from the source electrode and the drain electrode by spacers.