IP Library Granted Patent US 12,706,439
Granted Patent B2
US 12,706,439 · App. 17/591,414 · Granted Aug 11, 2026

Vertical cavity surface emitting laser, head gimbal assembly, and fabrication process

Inventors: Takuya Matsumoto (San Jose, CA); Barry C. Stipe (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
H01S5/04256G11B5/4826G11B5/4866G11B13/08H01S5/0201H01S5/02326H01S5/0233H01S5/0237H01S5/04257H01S5/18394H01S5/423G11B2005/0021H01S5/183
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,706,439
App. No.
17/591,414
Filed
Feb 2, 2022
Granted
Aug 11, 2026
Kind
B2
Art Unit
2828
USPC
438/33
Abstract

Embodiments of the present disclosure generally relate to a vertical cavity surface emitting laser (VCSEL), a head gimbal assembly for mounting a VCSEL, devices incorporating such articles, and to a process for forming a VCSEL. In an embodiment, a process for forming a VCSEL device is provided. The process includes forming a trench in a substrate, forming two laser diode electrodes in the trench, and after forming the two laser diode electrodes, cutting the substrate along the trench to form a VCSEL, the VCSEL comprising a chip for mounting on a slider, the chip having six surfaces, wherein a first surface of the chip is for facing the slider, a second surface of the chip is opposite the first surface, the two laser diode electrodes being positioned in any combination on one or more of a third surface, a fourth surface, a fifth surface, or a sixth surface.

Claims (58)

1 . A process for forming a vertical cavity surface emitting laser (VCSEL) device, comprising:

forming a trench in a first surface of a substrate, the trench comprising a first surface perpendicular to the first surface of the substrate, a second surface parallel to the first surface, and a third surface perpendicular to the first and second surfaces of the trench, the third surface of the trench connecting the first and second surfaces of the trench;

forming two laser diode electrodes in the trench, wherein forming the two laser diode electrodes in the trench comprises:

depositing a seed layer comprising a conductive material on the substrate, the seed layer being disposed on the first, second, and third surfaces of the trench;

patterning a photoresist material on the seed layer, wherein the photoresist material is disposed within at least a portion of the trench; and

depositing a metal containing material on at least a portion of the seed layer that is free of the photoresist material, the metal containing material being disposed over the first, second, and third surfaces of the trench, and over a portion of the first surface of the substrate adjacent to the first and second surfaces of the trench; and

after forming the two laser diode electrodes, cutting the substrate along the trench to form a VCSEL, the VCSEL comprising:

a chip for mounting on a slider, the chip having six surfaces, wherein:

a first surface of the chip is for facing the slider;

a second surface of the chip is opposite the first surface of the chip; and

the two laser diode electrodes being positioned in any combination on one or more of a third surface of the chip, a fourth surface of the chip, a fifth surface of the chip, or a sixth surface of the chip.

2 . The process of claim 1 , wherein:

the seed layer is deposited by sputtering, atomic layer deposition, ion beam deposition, or combinations thereof; and

metal containing material is deposited by plating, sputtering, vacuum evaporation, ion beam deposition, or combinations thereof.

3 . The process of claim 2 , wherein the seed layer is deposited by ion beam deposition.

4 . The process of claim 1 , wherein the seed layer comprises copper, gold, chromium, titanium, nickel, ruthenium, rhodium, iridium, palladium, platinum, or combinations thereof.

5 . The process of claim 1 , wherein forming the trench in the substrate comprises forming a single trench.

6 . The process of claim 1 , wherein forming the trench in the substrate comprises forming a first trench and a second trench, the first trench for disposing a first laser diode electrode of the two laser diode electrodes therein, the second trench for disposing a second laser diode electrode of the two laser diode electrodes therein.

7 . The process of claim 1 , wherein the substrate comprises Ga, As, Al, In, or combinations thereof.

8 . The process of claim 1 , wherein the substrate is selected from the group consisting of GaAs, AlAs, AlGaAs, InGaAs, InGaAsN, GaAsN, GaAsP, InP, and InGaAsP.

9 . The process of claim 1 , wherein at least a portion of the trench remains after forming the two laser diode electrodes in the trench.

10 . A process for forming a vertical cavity surface emitting laser (VCSEL) device, comprising:

etching one or more trenches in a first surface of a substrate, each trench comprising a first surface, a second surface parallel to the first surface, and a third surface perpendicular to the first and second surfaces of the trench, the third surface of the trench connecting the first and second surfaces of the trench;

forming two laser diode electrodes in the one or more trenches, wherein forming the two laser diode electrodes in the one or more trenches comprises:

depositing a seed layer comprising a conductive material on the substrate, the seed layer being disposed on the first, second, and third surfaces of each trench;

patterning a photoresist material on the seed layer, wherein the photoresist material is disposed within at least a portion of each of the one or more trenches; and

depositing a metal containing material on at least a portion of the seed layer that is free of the photoresist material, the metal containing material being disposed over the first, second, and third surfaces of each trench, and over a portion of the first surface of the substrate adjacent to the first and second surfaces of the trench;

after forming the two laser diode electrodes, cutting the substrate along the one or more trenches to form a VCSEL, the VCSEL comprising:

a chip for mounting on a slider, the chip having six surfaces, wherein:

a first surface of the chip is for facing the slider;

a second surface of the chip is opposite the first surface of the chip; and

the two laser diode electrodes being positioned in any combination on one or more of a third surface of the chip, a fourth surface of the chip, a fifth surface of the chip, or a sixth surface of the chip.

11 . The process of claim 10 , wherein etching the one or more trenches in the substrate comprises:

etching a first trench of the one or more trenches; and

etching a second trench of the one or more trenches.

12 . The process of claim 11 , wherein:

at least a portion of a first laser diode electrode of the two laser diode electrodes is positioned in the first trench; and

at least a portion of a second laser diode electrode of the two laser diode electrodes is positioned in the second trench.

13 . The process of claim 11 , wherein etching the first trench, etching the second trench or both comprises performing a reactive ion etch with a chlorine containing material.

14 . The process of claim 10 , wherein forming the two laser diode electrodes in the one or more trenches comprises:

depositing a seed layer comprising a conductive material on the substrate; and

depositing a metal containing material on at least a portion of the seed layer.

15 . A process for forming a vertical cavity surface emitting laser (VCSEL) device, comprising:

etching one or more trenches formed therein in a first surface of a substrate, each of the one or more trenches comprising a first surface, a second surface parallel to the first surface of the trench, and a third surface perpendicular to the first and second surfaces of the trench, the third surface connecting the first and second surfaces of the trench;

depositing a seed layer comprising a conductive material on the substrate, the seed layer being disposed on the first, second, and third surfaces of each of the one or more trenches;

patterning a photoresist material on the seed layer, wherein the photoresist material is disposed within at least a portion of each of the one or more trenches;

depositing a metal containing material on at least a portion of the seed layer that is free of the photoresist material, the metal containing material being disposed over the first, second, and third surfaces of each of the one or more trenches, and over a portion of the first surface of the substrate adjacent to the first and second surfaces of the trench;

removing the photoresist material and a portion of the seed layer from the substrate; and

cutting the substrate along the one or more trenches of the substrate after removing the photoresist material and the portion of the seed layer to form a VCSEL, the VCSEL comprising:

a chip for mounting on a slider, the chip having six surfaces, wherein:

a first surface of the chip is for facing the slider;

a second surface of the chip is opposite the first surface of the chip; and

two laser diode electrodes being positioned in any combination on one or more of a third surface of the chip, a fourth surface of the chip, a fifth surface of the chip, or a sixth surface of the chip, the two laser diode electrodes formed from the seed layer and the metal containing material.

16 . The process of claim 15 , wherein the one or more trenches is at least two trenches, and wherein the at least two trenches have different depths.

17 . The process of claim 15 , wherein the seed layer is deposited by ion beam deposition.

18 . The process of claim 15 , wherein the seed layer comprises copper, gold, chromium, titanium, nickel, ruthenium, rhodium, iridium, palladium, platinum, or combinations thereof.

19 . The process of claim 15 , further comprising depositing a resist coating on the substrate, the seed layer, the metal containing material, or combinations thereof before dicing the substrate and after removing the photoresist material and the portion of the seed layer.

20 . The process of claim 15 , wherein an insulating layer is deposited over at least a portion of the substrate prior to depositing the seed layer.

Assignments (3)
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2022
From: MATSUMOTO, TAKUYA; STIPE, BARRY CUSHING
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058873/0545 →
Continuity (3)
Provisional Application 63211288 · Jun 16, 2021
Provisional Application 63211302 · Jun 16, 2021
Related Publication 20220407287A1 · Dec 22, 2022
References Cited (73)
US 7627018B1 · Guilfoyle et al. · 2009 [cited by applicant]
US 8107326B1 · Hirano · 2012 [cited by examiner]
US 8116171B1 · Lee · 2012 [cited by applicant]
US 8139448B1 · Hirano et al. · 2012 [cited by applicant]
US 8184507B1 · Hirano et al. · 2012 [cited by applicant]
US 8343364B1 · Gao et al. · 2013 [cited by applicant]
US 8804468B2 · Zhao et al. · 2014 [cited by applicant]
US 8908480B1 · Krichevsky · 2014 [cited by applicant]
US 9065236B2 · Goulakov et al. · 2015 [cited by applicant]
US 9196278B1 · Tatah et al. · 2015 [cited by applicant]
US 9286920B1 · Hu et al. · 2016 [cited by applicant]
US 10127938B2 · Goggin et al. · 2018 [cited by applicant]
US 10229704B2 · Blaber et al. · 2019 [cited by applicant]
US 10242702B1 · Peng · 2019 [cited by applicant]
US 10262683B2 · Staffaroni et al. · 2019 [cited by applicant]
US 10403315B2 · Matsumoto et al. · 2019 [cited by applicant]
US 10636442B2 · Matsumoto et al. · 2020 [cited by applicant]
US 11574647B1 · Yu et al. · 2023 [cited by applicant]
US 11798582B2 · Puri et al. · 2023 [cited by applicant]
US 11894031B1 · Jin et al. · 2024 [cited by applicant]
US 12119032B1 · Matsumoto et al. · 2024 [cited by applicant]
US 20030169796A1 · Nakamura · 2003 [cited by examiner]
US 20050167830A1 · Chang · 2005 [cited by examiner]
US 20050183960A1 · Andideh et al. · 2005 [cited by applicant]
US 20060220192A1 · Kurachi · 2006 [cited by examiner]
US 20060251137A1 · Sung et al. · 2006 [cited by applicant]
US 20070164279A1 · Lin · 2007 [cited by examiner]
US 20070201530A1 · Rhee · 2007 [cited by examiner]
US 20080054457A1 · Lin · 2008 [cited by examiner]
US 20090154514A1 · Oh et al. · 2009 [cited by applicant]
US 20090225636A1 · Hirano et al. · 2009 [cited by applicant]
US 20100085664A1 · Hirata et al. · 2010 [cited by applicant]
US 20110135318A1 · Takeda et al. · 2011 [cited by applicant]
US 20110216635A1 · Matsumoto · 2011 [cited by applicant]
US 20120113770A1 · Stipe · 2012 [cited by applicant]
US 20120230361A1 · Adachi et al. · 2012 [cited by applicant]
US 20130286799A1 · Zhu et al. · 2013 [cited by applicant]
US 20140098652A1 · Tomiyama et al. · 2014 [cited by applicant]
US 20160284370A1 · Takayama et al. · 2016 [cited by applicant]
US 20160300592A1 · Kawakami et al. · 2016 [cited by applicant]
US 20170256277A1 · Peng · 2017 [cited by applicant]
US 20180335575A1 · Gudeman · 2018 [cited by applicant]
US 20200091679A1 · Furuyama · 2020 [cited by examiner]
US 20200144792A1 · Dummer · 2020 [cited by applicant]
US 20210201942A1 · Zhao et al. · 2021 [cited by applicant]
US 20210398556A1 · Stipe et al. · 2021 [cited by applicant]
US 20210398557A1 · Stipe et al. · 2021 [cited by applicant]
US 20220189507A1 · Stipe et al. · 2022 [cited by applicant]
US 20220407292A1 · Matsumoto · 2022 [cited by applicant]
US 20240296866A1 · Xu et al. · 2024 [cited by applicant]
CN 103325389A · 2013 [cited by applicant]
CN 104269739A · 2015 [cited by applicant]
CN 105144511A · 2015 [cited by applicant]
CN 110679049A · 2020 [cited by applicant]
CN 116917988A · 2023 [cited by applicant]
CN 116982227A · 2023 [cited by applicant]
JP H0669605A · 1994 [cited by applicant]
JP 2000101020A · 2000 [cited by applicant]
JP 200322967A · 2003 [cited by applicant]
JP 2008152869A · 2008 [cited by applicant]
JP 2011096857A · 2011 [cited by applicant]
JP 2011124314A · 2011 [cited by applicant]
JP 2013098404A · 2013 [cited by applicant]
JP 2020046511A · 2020 [cited by applicant]
International Search Report and Written Opinion for International Application No. PCT/US2022/016654 dated Jun. 27, 2022. [cited by applicant]
International Search Report and Written Opinion for International Application No. PCT/US2022/019987 dated Aug. 9, 2022. [cited by applicant]
U.S. Appl. No. 18/229,779, filed Aug. 3, 2023. [cited by applicant]
International Search Report and Written Opinion for Application No. PCT/US2024/012257 dated May 17, 2024. [cited by applicant]
Datta, Anurup et al., “Improved Near-Field Transducer Design for Heat-Assisted Magnetic Recording”, IEEE Transactions On Magnetics, vol. 52, No. 12, Dec. 2016, pp. 1-6. [cited by applicant]
Zhou, Nan et al., “Plasmonic near-field transducer for heat-assisted magnetic recording”, Science Wise Publishing & De Gruyter, 2014, pp. 141-155. [cited by applicant]
Challener, W. A. et al., “Heat-assisted magnetic recording by a near-field transducer with efficient optical energy transfer”, Nature Photonics, Mar. 2009, pp. 220-224. [cited by applicant]
Kryder, Mark H. et al., “Heat Assisted Magnetic Recording”, Proceedings of the IEEE, vol. 96, No. 11, Nov. 2008, pp. 1-27. [cited by applicant]
Du, Tianxiang et al., “A Novel Design of Capacitive Plasmonic Near Field Transducer”, Applied Physics, Jun. 2024, pp. 1-4. [cited by applicant]