IP Library › Granted Patent US 12,362,241
Granted Patent B2
US 12,362,241 · App. 17/644,801 · Granted Jul 15, 2025

Semiconductor structure and method for forming a semiconductor structure

Inventors: Richard Geiger (Munich, DE); Klaus Herold (Munich, DE); Harald Gossner (Riemerling, DE); Martin Ostermayr (Woerth, DE); Georgios Panagopoulos (Munich, DE); Johannes Rauh (Kirchseeon, DE); Joachim Singer (Neubiberg, DE); Thomas Wagner (Regelsbach, DE)
Assignee: Intel corporation
H01L22/32H01L23/481
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Quick Facts
Patent No.
US 12,362,241
App. No.
17/644,801
Granted
Jul 15, 2025
Kind
B2
Abstract

A semiconductor structure is provided. The semiconductor structure includes a plurality of transistors arranged at a front side of a semiconductor substrate and a test structure located at the front side of the semiconductor substrate. Further, the semiconductor structure comprises a first electrically conductive connection extending from the test structure through the semiconductor substrate to a backside test pad arranged at a backside of the semiconductor substrate.

Claims (61)

1. A semiconductor structure, comprising:

a plurality of transistors located at a front side of a semiconductor substrate;

a test structure located at the front side of the semiconductor substrate;

a first electrically conductive connection extending from the test structure through the semiconductor substrate to a backside test pad arranged at a backside of the semiconductor substrate.

2. The semiconductor structure according to claim 1 , wherein

the first electrically conductive connection comprises at least a part of a buried line arranged in a trench extending into the semiconductor substrate.

3. The semiconductor structure according to claim 2 , wherein

the first electrically conductive connection comprises a through semiconductor via extending from the backside of the semiconductor substrate to the buried line.

4. The semiconductor structure according to claim 1 , wherein

the first electrically conductive connection comprises a portion located in a front-end-of-line layer located on top of the semiconductor substrate.

5. The semiconductor structure according to claim 1 , wherein

the semiconductor structure is a semiconductor wafer or a semiconductor die.

6. The semiconductor structure according to claim 1 , wherein

the semiconductor structure is a semiconductor wafer and wherein the test structure is located in a kerf region of the semiconductor wafer.

7. The semiconductor structure according to claim 1 , wherein

a maximal dimension of the backside test pad is at most 100 μm and at least 10 μm.

8. The semiconductor structure according to claim 1 , wherein

the test structure comprises at least one element of the group of:

a transistor;

a resistor;

a diode;

a capacitor;

a metal layer; and

a via.

9. The semiconductor structure according to claim 1 , wherein:

the test structure comprises a first terminal and a second terminal, wherein the first electrically conductive connection is connected to the first terminal, wherein a second electrically conductive connection extends from the second terminal to a front side test pad arranged at the front side of the semiconductor substrate.

10. The semiconductor structure according to claim 9 , wherein

a third electrically conductive connection extends from the first terminal to a further front side test pad arranged at the front side of the semiconductor substrate.

11. The semiconductor structure according to claim 9 , wherein

a fourth electrically conductive connection extends from the second terminal through the semiconductor substrate to a further backside test pad arranged at the backside of the semiconductor substrate.

12. The semiconductor structure according to claim 1 , further comprising:

a further test structure arranged at the front side of the semiconductor substrate; and

a second electrically conductive connection extending from the further test structure to a front side test pad arranged at the front side of the semiconductor substrate.

13. The semiconductor structure according to claim 9 , wherein

the second electrically conductive connection comprises a portion located in a front side wiring layer stack formed on the front side of the semiconductor substrate.

14. The semiconductor structure according to claim 9 , wherein

the front side test pad laterally overlaps with the backside test pad.

15. The semiconductor structure according to claim 12 , wherein

a third electrically conductive connection extends from the further test structure to a further front side test pad arranged at the front side of the semiconductor substrate.

16. The semiconductor structure according to claim 10 , wherein

the third electrically conductive connection comprises a portion located in a front side wiring layer stack formed on the front side of the semiconductor substrate.

17. The semiconductor structure according to claim 12 , wherein

the test structure comprises a first terminal and a second terminal, wherein the first electrically conductive connection is connected to the first terminal, wherein

a fourth electrically conductive connection extends from the second terminal of the test structure through the semiconductor substrate to a further backside test pad arranged at the backside of the semiconductor substrate.

18. The semiconductor structure according to claim 11 , wherein

the fourth electrically conductive connection comprises at least a part of a buried line arranged in a trench extending into the semiconductor substrate.

19. The semiconductor structure according to claim 18 , wherein

the fourth electrically conductive connection comprises a through semiconductor via extending from the backside of the semiconductor substrate to the buried line.

20. The semiconductor structure according to claim 11 , wherein

the further front side test pad laterally overlaps with the further backside test pad.

21. The semiconductor structure according to claim 12 , wherein

a wiring layer stack comprises an intermediate layer, wherein the test structure and all backside test pads connected to the test structure are located at a first side of the intermediate layer, and wherein the further test structure and all front side test pads connected to the further test structure are located at a second, opposite side of the intermediate layer.

22. A method for forming a semiconductor structure, comprising:

forming a plurality of transistors located at a front side of a semiconductor substrate, a test structure at the front side of the semiconductor substrate, and a first electrically conductive connection extending from the test structure through the semiconductor substrate to a backside of the semiconductor substrate; and

forming a backside test pad at the backside of the semiconductor substrate electrically connected to the first electrically conductive connection.

23. The method according to claim 22 , wherein

forming the first electrically conductive connection comprises forming a trench extending into the semiconductor substrate and forming a buried line in the trench.

24. An electronic device comprising a semiconductor structure, comprising:

a plurality of transistors located at a front side of a semiconductor substrate;

a test structure located at the front side of the semiconductor substrate;

a first electrically conductive connection extending from the test structure through the semiconductor substrate to a backside test pad arranged at a backside of the semiconductor substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076063/0964 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2021
From: GEIGER, RICHARD; HEROLD, KLAUS; GOSSNER, HARALD; OSTERMAYR, MARTIN; PANAGOPOULOS, GEORGIOS; RAUH, JOHANNES; SINGER, JOACHIM; WAGNER, THOMAS
To: INTEL CORPORATION
Reel/Frame 058412/0074 →
Continuity (1)
Related Publication 20230197537A1 · Jun 22, 2023
References Cited (2)
US 20130342231A1 · Alfano · 2013 [cited by examiner]
US 20150228547A1 · Shih · 2015 [cited by examiner]