Electronic devices with a low dielectric constant
An interconnect layer for a device and methods for fabricating the interconnect layer are provided. The interconnect layer includes first metal structures arranged in a first array in the interconnect layer and second metal structures, arranged in a second array in the interconnect layer. The second array includes at least one metal structure positioned between two metal structures of the first metal structures. The interconnect layer also includes a spacer material formed around each of the first metal structures and the second metal structures and air gaps formed in the spacer material on each side of the first metal structures.
1. An interconnect layer for a device comprising:
a plurality of first metal structures arranged in a first array in the interconnect layer, wherein the plurality of first metal structures extend between a first plane and a second plane of the interconnect layer;
a plurality of second metal structures, arranged in a second array in the interconnect layer, wherein the second array comprises at least one metal structure of the plurality of second metal structures positioned between two metal structures of the plurality of first metal structures, wherein:
the plurality of second metal structures extend between the first plane and the second plane of the interconnect layer, and
the plurality of second metal structures comprise a different composition from the plurality of first metal structures,
a spacer material formed around each of the plurality of first metal structures and the plurality of second metal structures; and
a plurality of air gaps formed in the spacer material on each side of the plurality of first metal structures.
2. The interconnect layer of claim 1 , wherein the spacer material comprises an interlayer dielectric (ILD) material.
3. The interconnect layer of claim 1 , further comprising one or more of:
a first liner formed on a bottom side of a respective metal structure of the plurality of first metal structures or of the plurality of second metal structures;
a second liner formed on a first sidewall of the respective metal structure; and
a third liner formed on a second sidewall of the respective metal structure.
4. The interconnect layer of claim 1 , further comprising a section of dielectric material filling a space in the interconnect layer not occupied by the first array, the second array, and the spacer material.
5. The interconnect layer of claim 1 , wherein the plurality of first metal structures comprise a first metal material, wherein the plurality of second metal structures comprise a second metal material, and wherein the first metal material is different than the second metal material.
6. The interconnect layer of claim 1 , wherein the plurality of second metal structures comprise a trapezoidal cross-sectional shape, where a bottom side of the trapezoidal cross-sectional shape of the plurality of second metal structures is a first length, wherein a top side of the trapezoidal cross-sectional shape of the plurality of second metal structures is a second length, and wherein the second length is longer than the first length.
7. The interconnect layer of claim 1 , wherein the first plane is part of a first etch stop layer on a first side of the interconnect layer and the second plane is part of a second etch stop layer on a second side of the interconnect layer.
8. A device comprising:
a first layer comprising one or more metal contacts; and
an interconnect layer formed on the first layer, comprising:
a plurality of first metal structures arranged in a first array in the interconnect layer, wherein the plurality of first metal structures extend between a first plane and a second plane of the interconnect layer;
a plurality of second metal structures, arranged in a second array in the interconnect layer, wherein the second array comprises at least one metal structure of the plurality of second metal structures positioned between two metal structures of the plurality of first metal structures, wherein:
the plurality of second metal structures extend between the first plane and the second plane of the interconnect layer, and
the plurality of second metal structures comprise a different composition from the plurality of first metal structures,
a spacer material formed around each of the plurality of first metal structures and the plurality of second metal structures; and
a plurality of air gaps formed in the spacer material on each side of the plurality of first metal structures.
9. The device of claim 8 , further comprising one or more of:
a first liner formed on a bottom side of a respective metal structure of the plurality of first metal structures or of the plurality of second metal structures;
a second liner formed on a first sidewall of the respective metal structure; and
a third liner formed on a second sidewall of the respective metal structure.
10. The device of claim 8 , further comprising a section of low-k dielectric material filling a space in the interconnect layer not occupied by the first array, the second array, and the spacer material.
11. The device of claim 8 , wherein the plurality of first metal structures comprise a first metal material, wherein the plurality of second metal structures comprise a second metal material, and wherein the first metal material is different than the second metal material.
12. The device of claim 8 , wherein the plurality of second metal structures comprise a trapezoidal cross-sectional shape, where a bottom side of the trapezoidal cross-sectional shape of the plurality of second metal structures is a first length, wherein a top side of the trapezoidal cross-sectional shape of the plurality of second metal structures is a second length, and wherein the second length is longer than the first length.
13. The device of claim 8 , wherein the first plane is part of a first etch stop layer on a first side of the interconnect layer and the second plane is part of a second etch stop layer on a second side of the interconnect layer.
14. A method comprising:
forming a first array of metal structures on a base structure;
depositing a first spacer material on the base structure and the first array of metal structures;
etching the first spacer material to form an array of structured spaces in the first spacer material;
forming a second array of metal structures using the array of structured spaces;
removing the first spacer material;
forming a spacer layer with a plurality of air gaps between the first array of metal structures and the second array of metal structures; and
processing the first array of metal structures, the second array of metal structures, and the spacer layer to form an interconnect layer for a device.
15. The method of claim 14 , wherein forming the first array of metal structures on the base structure comprises:
forming a first liner layer on the base structure;
forming a first metal layer on the first liner layer;
forming a first mask layer on the first metal layer;
forming an low temperature oxide (LTO) layer on the first metal layer; and
etching the first liner layer, the first metal layer, the first mask layer, and the LTO layer to form the first array of metal structures.
16. The method of claim 14 , wherein forming the second array of metal structures comprises:
depositing a second liner layer within at least the array of structured spaces;
depositing a second metal material within at least the array of structured spaces; and
removing a portion of the deposited second metal material to form the second array of metal structures.
17. The method of claim 14 , further comprising:
depositing a low-k material on a portion of the base structure not occupied by the first array of metal structures, the second array of metal structures, and the spacer layer prior to processing the first array of metal structures, the second array of metal structures, and the spacer layer to form the interconnect layer.
18. The method of claim 14 , wherein the base structure comprises:
one or more metal contacts in contact with the interconnect layer; and
a base etch stop layer in contact with the interconnect layer; and
wherein the method further comprises:
depositing an interconnect etch stop cap layer on the first array of metal structures, the second array of metal structures, and the spacer layer.
19. The method of claim 14 , wherein forming the first array of metal structures comprises a first litho-etch process, and wherein forming the second array of metal structures comprises a second litho-etch process.
20. The method of claim 14 , wherein the first array of metal structures comprise a first metal material, wherein the second array of metal structures comprise a second metal material, and wherein the first metal material is different than the second metal material.