Enhanced linerless vias
A via connection layer for an electronic package and method for fabricating a via connection layer are provided. The via connection layer includes asymmetric via(s) formed in the via connection layer. The asymmetric via include a first sidewall with a first slope angle in a first direction and a second sidewall, where the second sidewall includes a second slope angle in the first direction.
1 . An electronic package comprising:
a first layer;
a second layer; and
a via layer between the first layer and the second layer comprising an asymmetric via formed in the via layer, wherein the asymmetric via comprises:
a top side that contacts the second layer;
a bottom side that contacts the first layer, wherein the bottom side is parallel with the top side;
a first sidewall with a first slope angle in a first direction between the first layer and the second layer; and
a second sidewall with a second slope angle in the first direction between the first layer and the second layer, wherein the second slope angle is different from the first slope angle.
2 . The electronic package of claim 1 , wherein the first layer comprises at least one source/drain contact, wherein the asymmetric via is positioned on a top surface of the at least one source/drain contact.
3 . The electronic package of claim 1 , wherein the second layer comprises one at least one metal line, wherein the at least one metal line is positioned on a top surface of the asymmetric via in the via layer.
4 . The electronic package of claim 1 , further comprising:
a source/drain region of a nanosheet layer, wherein the first layer is formed on the source/drain region, wherein the first layer and the via layer provide an electrical connection between the nanosheet layer and the second layer.
5 . The electronic package of claim 1 , wherein the via layer comprises a plurality of additional asymmetric vias formed in the via layer.
6 . The electronic package of claim 1 , wherein the bottom side comprises a bottom width and the top side comprises a top width, wherein the bottom width is larger than the top width.
7 . The electronic package of claim 1 , further comprising a plurality of symmetric vias in the via layer, wherein a cross-sectional profile is symmetrical for the plurality of symmetric vias.
8 . A via connection layer comprising:
an asymmetric via formed in the via connection layer, wherein the asymmetric via comprises:
a top side that contacts a second layer;
a bottom side that contacts a first layer, wherein the bottom side is parallel with the top side;
a first sidewall, where the first sidewall comprises a first slope angle in a first direction; and
a second sidewall, wherein the second sidewall comprises a second slope angle in the first direction, wherein the second slope angle is different from the first slope angle.
9 . The via connection layer of claim 8 , wherein the asymmetric via is formed on a top surface of at least one source/drain contact.
10 . The via connection layer of claim 9 , wherein at least one metal line is formed on the via connection layer, wherein the at least one metal line is formed on a top surface of the asymmetric via in the via connection layer.
11 . The via connection layer of claim 10 , further comprising:
a source/drain region of a nanosheet layer in connection with the via connection layer through at least one source/drain contact, wherein the via connection layer provides an electrical connection between the nanosheet layer and the at least one metal line.
12 . The via connection layer of claim 8 , wherein the via connection layer comprises a plurality of additional asymmetric vias.
13 . The via connection layer of claim 8 , wherein the bottom side comprises a bottom width and the top side comprises a top width, wherein the bottom width is larger than the top width.
14 . The via connection layer of claim 8 , further comprising a plurality of symmetric vias in the via connection layer, wherein a cross-sectional profile is symmetrical for the plurality of symmetric vias.