CMOS devices containing asymmetric contact via structures and method of making the same

1. A CMOS device, comprising:

a p-type field effect transistor containing p-doped active regions;

an n-type field effect transistor containing n-doped active regions;

a silicon oxide layer overlying the n-type field effect transistor and not overlying the p-type field effect transistor;

boron-doped epitaxial pillar structures contacting a top surface of, and epitaxially aligned to, a respective one of the p-doped active regions;

first active region contact via structures contacting a top surface of a respective one of the boron-doped epitaxial pillar structures; and

second active region contact via structures contacting a top surface of a respective one of the n-doped active regions.

2. The CMOS device of claim 1 , further comprising:

a first silicon oxide liner contacting top surfaces of the p-doped active regions and the n-doped active regions;

a first silicon nitride liner overlying the first silicon oxide liner and extending over the p-type field effect transistor and the n-type field effect transistor;

a second silicon oxide liner which comprises the silicon oxide layer overlying a portion of the first silicon nitride liner over the n-type field effect transistor and not overlying the p-type field effect transistor;

a second silicon nitride liner overlying the second silicon oxide liner over the n-type field effect transistor and contacting the first silicon nitride liner over the p-type field effect transistor; and

a planarization silicon oxide layer overlying the second silicon nitride liner.

3. The CMOS device of claim 2 , wherein:

the boron-doped epitaxial pillar structures protrude through the first silicon oxide liner, the first silicon nitride liner, and the second silicon nitride liner;

the first active region contact via structures extend through the planarization silicon oxide layer to contact the top surface of the respective one of the boron-doped epitaxial pillar structures; and

the second active region contact via structures extend through the planarization silicon oxide layer, the second silicon nitride liner, the second silicon oxide liner, the first silicon nitride liner, and the first silicon oxide liner to contact the top surface of the respective one of the n-doped active regions.

4. The CMOS device of claim 2 , wherein:

the second silicon oxide liner applies tensile stress to the n-type field effect transistor;

the second silicon nitride liner applies compressive stress to the p-type field effect transistor;

each of the boron-doped epitaxial pillar structures has a respective sidewall having a first taper angle with respective to a vertical direction that is perpendicular to a top surface of the semiconductor substrate;

each of the first active region contact via structures has a respective sidewall having a second taper angle with respect to the vertical direction; and

the second taper angle is the same as the first taper angle.

5. The CMOS device of claim 2 , wherein each of the first active region contact via structures and the second active region contact via structures comprises:

a respective metallic barrier liner having a same first material composition and a same thickness; and

a respective metal fill material portion having a same second metal composition.

6. The CMOS device of claim 2 , wherein a planar top surface of a first portion of the second silicon nitride liner that overlies the p-type field effect transistor and a planar top surface of a second portion of the second silicon nitride liner that overlies the n-type field effect transistor and the second silicon oxide liner are within a same horizontal plane as the top surface of the planarization silicon oxide layer.

7. The CMOS device of claim 6 , further comprising a contact level dielectric layer overlying the planarization silicon oxide layer,

wherein:

a portion of the second silicon nitride liner located between a gate electrode of the n-type field effect transistor and the contact level dielectric layer has a lesser thickness than a portion of the second silicon nitride liner located between a gate electrode of the p-type field effect transistor and the contact level dielectric layer; and

top surfaces of the first active region contact via structures and the second active region contact via structures are within a same horizontal plane as a top surface of the contact level dielectric layer.

8. The CMOS device of claim 2 , wherein:

the p-doped active regions include boron atoms at a first average atomic concentration;

the boron-doped epitaxial pillar structures include boron atoms at a second average atomic concentration that is different from the first average atomic concentration;

a horizontal portion of the second silicon oxide liner is at least twice as thick as a horizontal portion of the first silicon oxide liner; and

a horizontal portion of the second silicon nitride liner overlying one of the n-doped active regions is at least twice as thick as a horizontal portion of the first silicon nitride liner.

9. The CMOS device of claim 1 , wherein:

top surfaces of the p-doped active regions and top surfaces of the n-doped active regions are within a horizontal plane that includes bottom surfaces of gate dielectrics of the p-type field effect transistor and the n-type field effect transistor; and

interfaces between the boron-doped epitaxial pillar structures and the p-doped active regions are recessed below the horizontal plane.

10. A three-dimensional NAND memory device, comprising:

the CMOS device of claim 1 located over a substrate;

an alternating stack of insulating layers and word lines located over the CMOS device; and

memory stack structures extending through the alternating stack and comprising a respective memory film and a vertical semiconductor channel.