IP Library › Granted Patent US 12,660,256
Granted Patent B2
US 12,660,256 · App. 18/356,851 · Granted Jun 16, 2026

High voltage field effect transistors with superjunctions and method of making the same

Inventor: Masashi Ishida (Yokkaichi, JP)
Assignee: Sandisk Technologies, Inc.
H10D62/111H10D30/0221H10D30/0285H10D62/104H10D62/153H10D62/154H10D62/157H10D62/158
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Quick Facts
Patent No.
US 12,660,256
App. No.
18/356,851
Granted
Jun 16, 2026
Kind
B2
Abstract

A field effect transistor includes a semiconductor channel having a doping of a first conductivity type, a gate structure overlying the semiconductor channel, a source region and a drain region, a source-side extension region including a source-side-extension plate portion and source-side-extension rail portions that overlie the source-side-extension plate portion, source-side counter-doped rails having a doping of the first conductivity type, a drain-side extension region including a drain-side-extension plate portion and drain-side-extension rail portions that overlie the drain-side-extension plate portion, and drain-side counter-doped rails interlaced with the drain-side-extension rail portions. A first superjunction structure is provided between the source-side counter-doped rails and the source-side extension region. A second superjunction structure is provided between the drain-side counter-doped rails and the drain-side extension region.

Claims (33)

1 . A field effect transistor, comprising:

a semiconductor channel having a doping of a first conductivity type;

a gate structure overlying the semiconductor channel and comprising a stack of a gate dielectric and a gate electrode;

a source region and a drain region having a doping of a second conductivity type and laterally spaced from the gate structure and from each other along a first horizontal direction, the second conductivity type being an opposite of the first conductivity type;

a source-side extension region laterally extending between the source region and a first bottom surface segment of the gate dielectric, having a doping of the second conductivity type, and including a source-side-extension plate portion and source-side-extension rail portions that overlie the source-side-extension plate portion;

source-side counter-doped rails having a doping of the first conductivity type, embedded in the source-side extension region, and interlaced with the source-side-extension rail portions along a second horizontal direction to provide a first superjunction structure;

a drain-side extension region laterally extending between the drain region and a second bottom surface segment of the gate dielectric, having a doping of the second conductivity type, and including a drain-side-extension plate portion and drain-side-extension rail portions that overlie the drain-side-extension plate portion; and

drain-side counter-doped rails having a doping of the first conductivity type, embedded in the drain-side extension region, and interlaced with the drain-side-extension rail portions along the second horizontal direction to provide a second superjunction structure.

2 . The field effect transistor of claim 1 , wherein:

the source-side-extension rail portions laterally extend along the first horizontal direction and have a respective uniform width along the second horizontal direction; and

the drain-side-extension rail portions laterally extend along the first horizontal direction and have a respective uniform width along the second horizontal direction.

3 . The field effect transistor of claim 2 , wherein the source-side counter-doped rails and the source-side-extension rail portions with a uniform periodicity along the second horizontal direction.

4 . The field effect transistor of claim 1 , wherein:

the source-side counter-doped rails are in contact with a sidewall of the source region; and

the drain-side counter-doped rails are in contact with a sidewall of the drain region.

5 . The field effect transistor of claim 1 , wherein:

the source-side counter-doped rails are not in direct contact with the semiconductor channel; and

the drain-side counter-doped rails are not in direct contact with the semiconductor channel.

6 . The field effect transistor of claim 1 , wherein:

top surfaces of the source-side counter-doped rails are located within a same horizontal plane as a top surface of the source-side extension region;

the source-side extension region has a first thickness; and

the source-side counter-doped rails have a second thickness that is less than the first thickness.

7 . The field effect transistor of claim 6 , wherein the source region has a third thickness that is less than the first thickness and is greater than the second thickness.

8 . The field effect transistor of claim 1 , further comprising a dielectric gate spacer that laterally surrounds the gate electrode, wherein each of the source-side counter-doped rails and the drain-side counter-doped rails has an areal overlap with a respective portion of the dielectric gate spacer in a plan view that is perpendicular to an interface between the semiconductor channel and the gate dielectric.

9 . The field effect transistor of claim 8 , wherein each of the source-side-extension rail portions and the source-side counter-doped rails are in contact with a respective segment of a bottom surface of the gate dielectric.

10 . The field effect transistor of claim 1 , wherein each of the source-side counter-doped rails and the drain-side counter-doped rails has an areal overlap with a respective portion of the gate electrode in a plan view that is perpendicular to an interface between the semiconductor channel and the gate dielectric.

11 . The field effect transistor of claim 1 , wherein each of the source-side counter-doped rails and the drain-side counter-doped rails does not have any areal overlap with the gate electrode in a plan view that is perpendicular to an interface between the semiconductor channel and the gate dielectric.

12 . The field effect transistor of claim 1 , wherein:

the semiconductor channel comprises dopants of the first conductivity type at a first average atomic concentration;

the source-side-extension plate portion comprises dopants of the second conductivity type at a second average atomic concentration that is higher than the first average atomic concentration; and

the source-side counter-doped rails comprise dopants of the first conductivity type at a third average atomic concentration that is higher than the second average atomic concentration.

13 . The field effect transistor of claim 12 , wherein the source-side-extension rail portions comprises dopants of the first conductivity type at the third average atomic concentration and comprises dopants of the second conductivity type at a fourth average atomic concentration that is higher than the third average atomic concentration.

14 . The field effect transistor of claim 12 , wherein the source region and the drain region comprises dopants of the second conductivity type at a higher average atomic concentration than the source-side-extension rail portions and the drain-side-extension rail portions.

Assignments (4)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2023
From: ISHIDA, MASASHI
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 065407/0448 →
Continuity (2)
Provisional Application 63481012 · Jan 23, 2023
Related Publication 20240250119A1 · Jul 25, 2024
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