High voltage field effect transistor with vertical current paths and method of making the same
A field effect transistor for a high voltage operation can include vertical current paths, which may include vertical surface regions of a pedestal semiconductor portion that protrudes above a base semiconductor portion. The pedestal semiconductor portion can be formed by etching a semiconductor material layer employing a gate structure as an etch mask. A dielectric gate spacer can be formed on sidewalls of the pedestal semiconductor portion. A source region and a drain region may be formed underneath top surfaces of the base semiconductor portion. Alternatively, epitaxial semiconductor material portions can be grown on the top surfaces of the base semiconductor portions, and a source region and a drain region can be formed therein. Alternatively, a source region and a drain region can be formed within via cavities in a planarization dielectric layer.
1. A semiconductor structure comprising:
a shallow trench isolation structure comprising a dielectric material embedded within a semiconductor material layer and laterally surrounding an upper portion of the semiconductor material layer, wherein the upper portion of the semiconductor material layer comprises a base semiconductor portion comprising a pair of top horizontal surfaces and a pedestal semiconductor portion located between the pair of top horizontal surfaces and vertically protruding above a horizontal plane including the pair of top horizontal surfaces;
a gate stack structure comprising a gate dielectric and a gate electrode and including a pair of sidewalls that are vertically coincident with a pair of sidewalls of the pedestal semiconductor portion;
a dielectric gate spacer contacting the pair of sidewalls of the gate stack structure and the pair of sidewalls of the pedestal semiconductor portion;
a pair of epitaxial semiconductor material portions located on and above the pair of top horizontal surfaces of the base semiconductor portion and epitaxially aligned to the base semiconductor portion, wherein the pair of epitaxial semiconductor material portions comprises a source region and a drain region; and
a shallow trench isolation spacer that comprises a same insulating material as the dielectric gate spacer, adjoined to the dielectric gate spacer, and contacts sidewalls of the shallow trench isolation structure that are located above the horizontal plane including the pair of top horizontal surfaces of the base semiconductor portion;
wherein an entirety of sidewalls of pair of epitaxial semiconductor material portions contacts a respective sidewall of the dielectric gate spacer or a respective sidewall of the shallow trench isolation spacer.
2. The semiconductor structure of claim 1 , wherein a bottom surface of the source region and a bottom surface of the drain region are located above a horizontal plane including the pair of top horizontal surfaces of the base semiconductor portion.
3. The semiconductor structure of claim 1 , wherein the dielectric gate spacer contacts peripheral portions of the pair of top horizontal surfaces of the base semiconductor portion.
4. The semiconductor structure of claim 1 , wherein:
a horizontal interface between the gate dielectric and the pedestal semiconductor portion is located above the horizontal plane including the pair of top horizontal surfaces of the base semiconductor portion; and
a vertical distance between the horizontal interface between the gate dielectric and the pedestal semiconductor portion and the horizontal plane including the pair of top horizontal surfaces of the base semiconductor portion is in a range from 100 nm to 2 microns.
5. The semiconductor structure of claim 1 , further comprising:
a dielectric liner continuously extending over and contacting a top surface of the source region, a top surface of the drain region, an outer sidewall of the dielectric gate spacer, and a top surface of the gate stack structure;
a planarization dielectric layer overlying the dielectric liner and having a planar top surface; and
contact via structures vertically extending through the planarization dielectric layer and the dielectric liner and contacting a respective one of the source region, the drain region, and the gate electrode.
6. The semiconductor structure of claim 1 , wherein:
the base semiconductor portion comprises a first single crystalline semiconductor material portion having a doping of a first conductivity type;
the pedestal semiconductor portion comprises of a second single crystalline semiconductor material potion having a doping of a second conductivity type that is an opposite of the first conductivity type; and
the source region and the drain region have a doping of the second conductivity type.
7. The semiconductor structure of claim 6 , wherein the first single crystalline semiconductor material portion and the second single crystalline semiconductor material portion have a same material composition and are epitaxially aligned to each other.
8. The semiconductor structure of claim 6 , wherein each of the pair of epitaxial semiconductor material portions comprises a respective extension region having a doping of the second conductivity type and contacting a bottom surface of a respective one of the source region and the drain region.
9. The semiconductor structure of claim 6 , wherein the second single crystalline semiconductor material potion contacts sidewalls of the dielectric gate spacer.
10. The semiconductor structure of claim 6 , wherein the pedestal semiconductor portion comprises a source extension region and a drain extension region having a doping of the second conductivity type, adjoined to a bottom surface of the gate dielectric, contacting a bottom surface of the dielectric gate spacer, and including a horizontally-extending region having a respective top surface within the horizontal plane including the pair of top horizontal surfaces.
11. The semiconductor structure of claim 6 , wherein the pair of epitaxial semiconductor material portions comprises:
a raised source extension region contacting a bottom surface of the source region and having a bottom surface located within the horizontal plane including the pair of top horizontal surfaces; and
a raised drain extension region contacting a bottom surface of the drain region and having a bottom surface located within the horizontal plane including the pair of top horizontal surfaces.
12. A semiconductor structure comprising:
a shallow trench isolation structure comprising a dielectric material embedded within a semiconductor material layer and laterally surrounding an upper portion of the semiconductor material layer, wherein the upper portion of the semiconductor material layer comprises a base semiconductor portion comprising a pair of top horizontal surfaces and a pedestal semiconductor portion located between the pair of top horizontal surfaces and vertically protruding above a horizontal plane including the pair of top horizontal surfaces;
a gate stack structure comprising a gate dielectric and a gate electrode and including a pair of sidewalls that are vertically coincident with a pair of sidewalls of the pedestal semiconductor portion;
a dielectric gate spacer contacting the pair of sidewalls of the gate stack structure and the pair of sidewalls of the pedestal semiconductor portion; and
a pair of epitaxial semiconductor material portions located on and above the pair of top horizontal surfaces of the base semiconductor portion and epitaxially aligned to the base semiconductor portion, wherein the pair of epitaxial semiconductor material portions comprises a source region and a drain region;
wherein:
the base semiconductor portion comprises a first single crystalline semiconductor material portion having a doping of a first conductivity type;
the pedestal semiconductor portion comprises of a second single crystalline semiconductor material potion having a doping of a second conductivity type that is an opposite of the first conductivity type;
the source region and the drain region have a doping of the second conductivity type;
the pedestal semiconductor portion comprises a source extension region and a drain extension region having a doping of the second conductivity type, adjoined to a bottom surface of the gate dielectric, contacting a bottom surface of the dielectric gate spacer, and including a horizontally-extending region having a respective top surface within the horizontal plane including the pair of top horizontal surfaces.