High voltage field effect transistors with self-aligned silicide contacts and methods for making the same
A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.
1. A semiconductor structure including a first field effect transistor, the first field effect transistor comprising:
a first doped well located within a substrate and embedding a first source region and a first drain region;
a first gate dielectric, a first gate electrode, and a dielectric capping mask overlying the first doped well, wherein the dielectric capping mask comprises a vertically-extending portion that laterally surrounds the first gate electrode, a top portion that overlies a peripheral region of a top surface of the first gate electrode, and a horizontally-extending portion that contacts a top surface of the first gate dielectric outside an area of the first gate electrode;
a source-side opening extending through the first gate dielectric and the horizontally-extending portion of the dielectric capping mask and overlying the first source region;
a drain-side opening extending through the first gate dielectric and the horizontally-extending portion of the dielectric capping mask and overlying the first drain region;
a first source-side metal-semiconductor alloy portion contacting a top surface of the first source region and located within the source-side opening; and
a first drain-side metal-semiconductor alloy portion contacting a top surface of the first drain region and located within the drain-side opening.
2. The semiconductor structure of claim 1 , wherein the first field effect transistor further comprises:
a source-side dielectric spacer located at a peripheral portion of the first source-side opening, wherein the first source-side metal-semiconductor alloy portion is laterally bounded by an inner sidewall of the source-side dielectric spacer; and
a drain-side dielectric spacer located at a peripheral portion of the first drain-side opening, wherein the first drain-side metal-semiconductor alloy portion is laterally bounded by an inner sidewall of the drain-side dielectric spacer.
3. The semiconductor structure of claim 2 , wherein the first field effect transistor further comprises:
a second doped well laterally surrounding and forming a p-n junction at an interface with the first doped well;
a well contact semiconductor region overlying the second doped well; and
a well contact metal-semiconductor alloy portion contacting the well contact semiconductor region.
4. The semiconductor structure of claim 3 , wherein:
the first field effect transistor further comprises a well contact dielectric spacer located on an outer sidewall of the first gate dielectric; and
the well contact metal-semiconductor alloy portion contacts the well contact dielectric spacer.
5. The semiconductor structure of claim 4 , wherein:
the well contact dielectric spacer, the source-side dielectric spacer, and the drain-side dielectric spacer have a same material composition and a same lateral thickness;
the first source-side metal-semiconductor alloy portion comprises platinum nickel silicide; and
the first drain-side metal-semiconductor alloy portion comprises platinum nickel silicide.
6. The semiconductor structure of claim 2 , wherein:
the top portion of the dielectric capping mask comprises an opening within an area of the first gate electrode;
an annular dielectric spacer contacts a sidewall of the opening within the top portion of the dielectric capping mask; and
a first gate metal-semiconductor alloy portion is located on a top surface of the first gate electrode and is laterally bounded by the annular dielectric spacer.
7. The semiconductor structure of claim 1 , wherein:
an outer sidewall of the first gate dielectric is vertically coincident with an outer sidewall of the dielectric capping mask;
a first inner sidewall of the first gate dielectric laterally surrounds the source-side opening and is vertically coincident with a first inner sidewall of the dielectric capping mask; and
a second inner sidewall of the first gate dielectric laterally surrounds the drain-side opening and is vertically coincident with a second inner sidewall of the dielectric capping mask.
8. The semiconductor structure of claim 1 , further comprising a second field effect transistor that comprises:
a second doped well located within the substrate and embedding a second source region and a second drain region;
a second gate dielectric, a second gate electrode, and a sidewall spacer overlying the second doped well;
a dielectric spacer laterally surrounding the sidewall spacer;
a second source-side metal-semiconductor alloy portion contacting a top surface of the second source region and contacting the dielectric spacer; and
a second drain-side metal-semiconductor alloy portion contacting a top surface of the second drain region and contacting the dielectric spacer.