Three-dimensional memory device with vertical field effect transistors and method of making thereof

1. A bonded assembly comprising a memory die and a logic die, wherein:

the memory die comprises a three-dimensional memory array;

the logic die comprises a logic-side substrate and at least one set of vertical field effect transistors;

each vertical field effect transistor within each set of vertical field effect transistors comprises a bottom doped semiconductor electrode, a vertical transistor channel, a gate dielectric which surrounds the vertical transistor channel, and a top doped semiconductor electrode;

each set of vertical field effect transistors comprises a respective gate electrode that laterally surrounds each of the gate dielectrics within a same set of vertical field effect transistors; and

at least one set of vertical field effect transistors is electrically connected to electrical nodes of the three-dimensional memory array through sets of metal bonding pads through which the memory die and the logic die are bonded to each other.

2. The bonded assembly of claim 1 , wherein:

the logic die comprises substrate field effect transistors including a respective semiconductor channel comprising a portion of, or comprising a same material as, the logic-side substrate; and

the bottom doped semiconductor electrodes of the at least one set of vertical field effect transistors are electrically connected to a first subset of the substrate field effect transistors via a first subset of lower logic-side metal interconnect structures embedded within lower logic-side dielectric material layers.

3. The bonded assembly of claim 2 , further comprising upper logic-side metal interconnect structures electrically connecting the top doped semiconductor electrodes of the at least one set of vertical field effect transistors to logic-side bonding pads within the sets of metal bonding pads, and embedded within upper logic-side dielectric material layers.

4. The bonded assembly of claim 2 , wherein the gate electrode of each set of vertical field effect transistors is electrically connected to a second subset of the substrate field effect transistors via a second subset of lower logic-side metal interconnect structures.

5. The bonded assembly of claim 1 , wherein the memory die comprises:

an alternating stack of insulating layers and electrically conductive layers located on a memory-side substrate;

memory openings vertically extending through the alternating stack; and

memory opening fill structures located within the memory openings and comprising a respective set of a memory film and a vertical semiconductor channel.

6. The bonded assembly of claim 5 , wherein the three-dimensional memory array comprises a three-dimensional array of memory elements that includes portions of the memory films that are located adjacent to a respective one of vertical semiconductor channels.

7. The bonded assembly of claim 5 , wherein the memory die comprises:

drain regions located within the memory opening fill structures and contacting an end portion of a respective one of the vertical semiconductor channels; and

bit lines electrically connected to a respective subset of the drain regions through a respective set of drain contact via structures,

wherein a subset of the top doped semiconductor electrodes of the at least one set of vertical field effect transistors is electrically connected to a respective one of the bit lines.

8. The bonded assembly of claim 7 , wherein the at least one set of vertical field effect transistors comprise:

a first set of vertical field effect transistors including a respective bottom doped semiconductor electrode that is electrically connected to a respective sense amplifier circuit located on the logic-side substrate; and

a second set of vertical field effect transistors including a respective bottom doped semiconductor electrode that is electrically connected to a bit line bias circuit located on the logic-side substrate.

9. The bonded assembly of claim 8 , wherein:

the logic die comprises upper logic-side metal interconnect structures located between the at least one set of vertical field effect transistors and the sets of metal bonding pads; and

the upper logic-side metal interconnect structures comprises upper-electrode-connection metal lines that are electrically connected to a respective set of a top doped semiconductor electrode within the first set of vertical field effect transistors and a top doped semiconductor electrode within the second set of vertical field effect transistors.

10. The bonded assembly of claim 8 , wherein at least 50% of a total area of the at least one set of vertical field effect transistors has an areal overlap with a total area including each sense amplifier circuit and each bit line bias circuit in a plan view.

11. The bonded assembly of claim 5 , wherein:

the electrically conductive layers comprise word lines of the three-dimensional memory array;

the memory die comprises layer contact via structures extending vertically through a dielectric material portion and contacting a surface of a respective one of the electrically conductive layers; and

a subset of the top doped semiconductor electrodes of the at least one set of vertical field effect transistors is electrically connected to a respective one of the word lines.

12. The bonded assembly of claim 1 , wherein:

the vertical transistor channels comprise a respective elemental semiconductor material or a respective III-V compound semiconductor material;

one of the bottom doped semiconductor electrode or the top doped semiconductor electrode of the vertical field effect transistor comprises a source region of the vertical field effect transistor; and

another of the bottom doped semiconductor electrode or the top doped semiconductor electrode comprises a drain region of the vertical field effect transistor.

13. The bonded assembly of claim 1 , wherein:

each bottom doped semiconductor electrode of the at least one set of vertical field effect transistors contacts a top surface of a respective lower logic-side metal interconnect structure within the logic die; and

each top doped semiconductor electrode of the at least one set of vertical field effect transistors contacts a bottom surface of a respective upper logic-side metal interconnect structure within the logic die.

14. A method of forming a bonded assembly, comprising:

providing the memory die comprising a three-dimensional memory array and memory-side bonding pads;

forming at least one set of vertical field effect transistors over a logic-side substrate, wherein each set of vertical field effect transistor is formed by:

forming bottom doped semiconductor electrodes embedded within lower logic-side dielectric material layers over the logic-side substrate,

forming a gate electrode including a plurality of vertically-extending openings therethrough, wherein the bottom doped semiconductor electrodes are exposed underneath the vertically-extending openings,

forming a combination of a cylindrical gate dielectric and a vertical transistor channel within each of the vertically-extending openings,

forming top doped semiconductor electrodes on the vertical transistor channels; and

forming logic-side bonding pads embedded in upper logic-side dielectric material layers and electrically connected to a respective one of the top doped semiconductor electrodes over the at least one set of vertical field effect transistors, whereby a logic die is provided; and

bonding the memory-side bonding pads with the logic-side bonding pads.

15. The method of claim 14 , further comprising:

forming substrate field effect transistors including a respective semiconductor channel comprising a portion of, or comprising a same material as, a logic-side substrate semiconductor layer in the logic-side substrate; and

forming lower logic-side metal interconnect structures within the lower logic-side dielectric material layers, wherein the bottom doped semiconductor electrodes of the at least one set of vertical field effect transistors are electrically connected to a first subset of the substrate field effect transistors via a first subset of lower logic-side metal interconnect structures embedded within lower logic-side dielectric material layers.

16. The method of claim 15 , further comprising forming upper logic-side metal interconnect structures embedded within upper logic-side dielectric material layers over the at least one set of vertical field effect transistors, wherein the upper logic-side metal interconnect structures electrically connect the top doped semiconductor electrodes of the at least one set of vertical field effect transistors to the logic-side bonding pads.

17. The method of claim 14 , wherein providing the memory die comprises forming the memory die by:

forming an alternating stack of insulating layers and spacer material layers over a memory-side substrate, wherein the spacer material layers are formed are, or are subsequently replaced with, electrically conductive layers;

forming memory openings through the alternating stack; and

forming memory opening fill structures within the memory openings, wherein each of the memory opening fill structures comprises a respective set of a memory film and a vertical semiconductor channel,

wherein the memory die comprises a three-dimensional memory array including a three-dimensional array of memory elements that includes portions of the memory films that are located adjacent to a respective one of vertical semiconductor channels.

18. The method of claim 17 , wherein forming the memory die comprises:

forming drain regions at an end portion of a respective one of the vertical semiconductor channels; and

forming bit lines over the memory opening fill structures, wherein each of the bit lines is electrically connected to a respective subset of the drain regions through a respective set of drain contact via structures,

wherein a subset of the top doped semiconductor electrodes of the at least one set of vertical field effect transistors is electrically connected to a respective one of the bit lines.

19. The method of claim 17 , wherein:

the method comprises forming sense amplifier circuits and bit line bias circuits on the logic-side substrate;

the at least one set of vertical field effect transistors comprise:

a first set of vertical field effect transistors including a respective bottom doped semiconductor electrode that is electrically connected to a respective one of the sense amplifier circuits, and

a second set of vertical field effect transistors including a respective bottom doped semiconductor electrode that is electrically connected to a respective one of the bit line bias circuits; and

the method comprises forming upper-electrode-connection metal lines that are electrically connected to a respective set of a top doped semiconductor electrode within the first set of vertical field effect transistors and a top doped semiconductor electrode within the second set of vertical field effect transistors.

20. The method of claim 17 , wherein:

the electrically conductive layers comprise word lines of the three-dimensional memory array;

the method comprises forming layer contact via structures directly on a surface of a respective one of the electrically conductive layers; and

a subset of the top doped semiconductor electrodes of the at least one set of vertical field effect transistors is electrically connected to a respective one of the word lines via mating pairs of the memory-side bonding pads and the logic-side bonding pads.