Cutoff gate electrodes for switches for a three-dimensional memory device and method of making the same

1. A semiconductor structure, comprising:

a first-conductivity-type well located in a semiconductor substrate;

a semiconductor active area region located adjacent to the a first-conductivity-type well;

a first transistor comprising a source region, a drain region, a channel region located between the source region and the drain region, a gate dielectric layer located over the channel region and a gate electrode located over the gate dielectric layer, wherein the transistor is located on the semiconductor active area region;

a cutoff gate electrode located over the semiconductor active area region, and between the first transistor and the first-conductivity-type well;

an array of memory devices located over the first transistor and comprising an array of memory elements, word lines, and bit lines;

a bit line switch array located on the semiconductor substrate and comprising a row of switches, wherein each of the switches comprises a sense circuit switch transistor located on a first side of a bit-line-connection contact via structure, the first transistor comprising an erase-voltage-connection switch transistor located on a second side of the bit-line-connection contact via structure, wherein the cutoff gate electrode is located between the erase-voltage-connection switch transistor and the first-conductivity-type well located adjacent to the bit line switch array; and

lower-level dielectric material layers embedding the bit-line-connection contact via structures of the switches and located between the first transistor and the array of memory devices, wherein a subset of the bit lines is electrically connected to a respective one of the switches through a respective bit-line-connection contact via structure,

wherein:

each of the switches is located on the respective semiconductor active area region that is a portion of the semiconductor substrate and is laterally surrounded by a respective portion of a shallow trench isolation structure; and

each of the switches comprises:

a drain region contacting the line-connection contact via structure;

a sense-circuit-side source region that is a source region of the sense circuit switch transistor; and

an erase-voltage-side source region that is a source region of the erase-voltage connection switch transistor, and

wherein:

an edge of the cutoff gate electrode extends past the edge of the semiconductor active area region and overlies the shallow trench isolation structure;

the first-conductivity-type well is laterally spaced from an interface between the respective semiconductor active area region and the shallow trench isolation structure; and

the first-conductivity-type well has an annular configuration and laterally surrounds the bit line switch array.

2. A semiconductor structure, comprising:

a first-conductivity-type well located in a semiconductor substrate;

a semiconductor active area region located adjacent to the a first-conductivity-type well;

a first transistor comprising a source region, a drain region, a channel region located between the source region and the drain region, a gate dielectric layer located over the channel region and a gate electrode located over the gate dielectric layer, wherein the transistor is located on the semiconductor active area region;

a cutoff gate electrode located over the semiconductor active area region, and between the first transistor and the first-conductivity-type well;

an array of memory devices located over the first transistor and comprising an array of memory elements, word lines, and bit lines;

a bit line switch array located on the semiconductor substrate and comprising a row of switches, wherein each of the switches comprises a sense circuit switch transistor located on a first side of a bit-line-connection contact via structure, the first transistor comprising an erase-voltage-connection switch transistor located on a second side of the bit-line-connection contact via structure, wherein the cutoff gate electrode is located between the erase-voltage-connection switch transistor and the first-conductivity-type well located adjacent to the bit line switch array; and

lower-level dielectric material layers embedding the bit-line-connection contact via structures of the switches and located between the first transistor and the array of memory devices, wherein a subset of the bit lines is electrically connected to a respective one of the switches through a respective bit-line-connection contact via structure,

wherein:

each of the switches is located on the respective semiconductor active area region that is a portion of the semiconductor substrate and is laterally surrounded by a respective portion of a shallow trench isolation structure; and

each of the switches comprises:

a drain region contacting the line-connection contact via structure;

a sense-circuit-side source region that is a source region of the sense circuit switch transistor; and

an erase-voltage-side source region that is a source region of the erase-voltage connection switch transistor, and

wherein the first-conductivity-type well comprises:

a base portion located under a horizontal plane including a bottom surface of the shallow trench isolation structure; and

an annular pedestal portion that laterally surrounds the shallow trench isolation structure and contacting an outer sidewall of the shallow trench isolation structure.

3. The semiconductor structure of claim 2 , further comprising:

another shallow trench isolation structure laterally surrounding the annular pedestal portion of the first-conductivity-type well and overlying, and contacting, an outer region of the base portion of the first-conductivity-type well; and

well contact via structures contacting a top surface of the annular pedestal portion of the first-conductivity-type well.

4. A semiconductor structure, comprising:

a first-conductivity-type well located in a semiconductor substrate;

a semiconductor active area region located adjacent to the a first-conductivity-type well;

a first transistor comprising a source region, a drain region, a channel region located between the source region and the drain region, a gate dielectric layer located over the channel region and a gate electrode located over the gate dielectric layer, wherein the transistor is located on the semiconductor active area region;

a cutoff gate electrode located over the semiconductor active area region, and between the first transistor and the first-conductivity-type well;

an array of memory devices located over the first transistor and comprising an array of memory elements, word lines, and bit lines;

a bit line switch array located on the semiconductor substrate and comprising a row of switches, wherein each of the switches comprises a sense circuit switch transistor located on a first side of a bit-line-connection contact via structure, the first transistor comprising an erase-voltage-connection switch transistor located on a second side of the bit-line-connection contact via structure, wherein the cutoff gate electrode is located between the erase-voltage-connection switch transistor and the first-conductivity-type well located adjacent to the bit line switch array;

lower-level dielectric material layers embedding the bit-line-connection contact via structures of the switches and located between the first transistor and the array of memory devices, wherein a subset of the bit lines is electrically connected to a respective one of the switches through a respective bit-line-connection contact via structure; and

lower-level metal interconnect structures embedded in the lower-level dielectric material layers,

wherein:

a first subset of the lower-level metal interconnect structures provides electrical connection between a sense-circuit-side source region of a respective sense circuit switch transistor and a respective sense circuit located on the semiconductor substrate; and

a second subset of the lower-level metal interconnect structures provides electrical connection between an erase-voltage-side source region of a respective erase-voltage-connection switch transistor and an erase voltage power supply circuit.

5. The semiconductor structure of claim 4 , wherein the array of memory devices comprises a three-dimensional memory array that includes:

an alternating stack of insulating layers and electrically conductive layers that comprise the word lines; and

memory stack structures vertically extending through the alternating stack and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel, wherein the bit lines are electrically connected to a respective subset of the vertical semiconductor channels.

6. The semiconductor structure of claim 5 , further comprising:

a dielectric material portion contacting sidewalls of the alternating stack; and

through-memory-level connection via structures vertically extending through the dielectric material portion and electrically connecting a respective pair of a line-connection contact via structure and a bit line.