Semiconductor package and method for manufacturing semiconductor package

1. A semiconductor package, comprising:

a first redistribution structure that, includes a first insulating layer and a first redistribution layer disposed below the first insulating layer;

a semiconductor chip disposed on the first redistribution structure, wherein the semiconductor chip includes a connection terminal electrically connected to the first redistribution layer and buried in the first insulating layer;

an encapsulant disposed on the first redistribution structure wherein the encapsulant contacts at least side surfaces of the semiconductor chip;

a second redistribution structure disposed on the encapsulant wherein the second redistribution structure includes a second redistribution layer; and

a through via that includes a pattern portion buried in the first insulating layer and electrically connected to the first redistribution layer, and a via portion that penetrates through the encapsulant and electrically connects the pattern portion and the second redistribution layer,

wherein the connection terminal and the pattern portion are located at a first level, and are electrically connected to each other at a second level that is lower than the first level,

wherein the connection terminal has a first side surface,

wherein the pattern portion has a second side surface facing the first side surface of the connection terminal in a first direction, and

wherein the first insulating layer fills between the first side surface and the second side surface in the first direction.

2. The semiconductor package of claim 1 , wherein a lower surface of the connection terminal and a lower surface of the pattern portion are located at different levels in a second direction perpendicular to the first direction.

3. The semiconductor package of claim 2 , wherein the lower surface of the pattern portion is located at a lower level from the lower surface of the connection terminal.

4. The semiconductor package of claim 1 , wherein the first side surface of the connection terminal and the second side surface of the pattern portion contact the first insulating layer,

wherein a second height of the second side surface of the pattern portion is greater than a first height of the first side surface of the connection terminal.

5. The semiconductor package of claim 4 , wherein the first height is from about 1 μm to about 6 μm, and

the second height is from about 5 μm to about 15 μm.

6. The semiconductor package of claim 1 , wherein the through-via has an integrated structure in which a boundary between the pattern portion and the via portion is not distinguishable.

7. The semiconductor package of claim 1 , wherein the via portion has a shape in which a side surface is tapered wherein a width of the is portion increases as the via portion approaches the pattern portion.

8. The semiconductor package of claim 1 , wherein at least a portion of an upper surface of the pattern portion is in contact with the encapsulant.

9. The semiconductor package of claim 1 , wherein the through-via further comprises a seed layer disposed on an upper surface of the pattern portion, and a side surface and an upper surface of the via portion.

10. The semiconductor package of claim 9 , wherein the seed layer comprises a metal that is substantially identical to that of the pattern portion and the via portion.

11. The semiconductor package of claim 1 , wherein the second redistribution structure further comprises a second insulating layer disposed between the encapsulant and the second redistribution layer, and a second redistribution via that penetrates through the second insulating layer and electrically connects the second redistribution layer and the through-via.

12. The semiconductor package of claim 11 , wherein the second insulating layer comprises a photosensitive resin.

13. The semiconductor package of claim 11 , wherein, the second redistribution structure further comprises a wiring layer disposed directly on an upper surface of the encapsulant and covered by the second insulating layer, and a wiring via that penetrates through a portion of the second insulating layer that covers the wiring layer and electrically connects the wiring layer and the second redistribution layer.

14. The semiconductor package of claim 13 , wherein the second redistribution layer has a multilayer structure in which a seed layer is disposed, and

the wiring layer has a single-layer structure.

15. A semiconductor package, comprising:

a redistribution structure that includes a first surface and a second surface opposite to the first surface, and an insulating layer and a redistribution layer disposed below the insulating layer;

a semiconductor chip disposed on the first surface of the redistribution structure, wherein the semiconductor chip includes a connection terminal electrically connected to the redistribution layer and is buried in the insulating layer; and

a through via that includes a pattern portion electrically connected to the redistribution layer and is buried in the insulating layer, and a via portion that extends from the pattern portion and is located on the insulating layer,

wherein a height in a direction perpendicular to the first surface of the pattern portion is greater than a height of the connection terminal, and

wherein the via portion has a shape in which a side surface is tapered wherein a width of the via portion increases as the via portion approaches the pattern portion.

16. The semiconductor package of claim 15 , wherein an upper surface of the pattern portion is substantially coplanar with the first surface of the semiconductor package.

17. The semiconductor package of claim 15 , wherein a height from the first surface to a lower surface of the pattern portion is greater than a height from the first surface to a lower surface of the connection terminal.

18. The semiconductor package of claim 15 , wherein the semiconductor chip further comprises a connection pad and a protective layer between the connection pad and the connection terminal, and

wherein the connection terminal has a metal post shape that penetrates through the protective layer and electrically connects to the connection pad.

19. The semiconductor package of claim 15 , wherein the connection terminal and the pattern portion are electrically connected to each other below the insulating layer.

20. A semiconductor package, comprising:

a redistribution structure that includes a first surface and a second surface opposite to the first surface, and an insulating layer and a redistribution layer disposed below the insulating layer;

a semiconductor chip disposed on the first surface of the redistribution structure, wherein the semiconductor chip includes a connection terminal electrically connected to the redistribution layer and buried in the insulating layer; and

a through via that includes a pattern portion electrically connected to the redistribution layer and buried in the insulating layer, and a via portion that extends from the pattern portion and is located on the insulating layer,

wherein a height of a portion of the pattern portion buried in the insulating layer is greater than a height of a portion of the connection terminal buried in the insulating layer, and

wherein the via portion has a shape in which a side surface is tapered wherein a width of the via portion increases as the via portion approaches the pattern portion.