NFET with aluminum-free work-function layer and method forming same
A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer forming a gate stack.
1 . A method comprising:
forming a dummy gate stack over a semiconductor region;
forming a source/drain region on a side of the dummy gate stack;
removing the dummy gate stack to form a trench;
depositing a gate dielectric layer extending into the trench;
depositing a metal-containing layer over the gate dielectric layer;
depositing a silicon-containing layer on the metal-containing layer, wherein the silicon-containing layer comprises elemental silicon, and the silicon-containing layer forms a ring encircling the semiconductor region,
wherein both of the metal-containing layer and the silicon-containing layer are work-function layers; and
performing a planarization process to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer forming a gate stack.
2 . The method of claim 1 , wherein the depositing the silicon-containing layer comprises soaking a corresponding wafer comprising the metal-containing layer in a silicon-containing process gas.
3 . The method of claim 1 , wherein after the metal-containing layer is deposited and before the silicon-containing layer is deposited, the metal-containing layer by itself has a p-type work function, and wherein the source/drain region is of n-type.
4 . The method of claim 3 , wherein at a time after the planarization process is performed, the metal-containing layer and the silicon-containing layer collectively have an n-type work-function equal to or smaller than about 4.55 eV.
5 . The method of claim 1 , wherein the depositing the metal-containing layer comprises depositing titanium nitride.
6 . The method of claim 1 further comprising depositing a glue layer over the silicon-containing layer, wherein the depositing the metal-containing layer, the depositing the silicon-containing layer, and the depositing the glue layer are in-situ performed in a same vacuum environment.
7 . The method of claim 1 , wherein the depositing the metal-containing layer is performed through atomic layer deposition.
8 . The method of claim 1 , wherein a distance from a bottom surface of the silicon-containing layer to the semiconductor region is smaller than about 3 nm.
9 . An method comprising:
forming an n-type source/drain region on a side of a semiconductor region;
forming a gate stack over the semiconductor region, the forming the gate stack comprising:
forming a gate dielectric;
depositing a metal-containing layer over the gate dielectric, wherein the metal-containing layer comprises:
a bottom portion over the gate dielectric;
a first sidewall portion and a second sidewall portion over and connecting to opposite ends of the bottom portion; and
forming a silicon layer over and physically contacting the metal-containing layer, wherein in a cross-section of the silicon layer, the silicon layer forms a ring encircling the semiconductor region; and
forming a filling metal over the silicon layer, wherein the forming the filling metal and the forming the silicon layer are in-situ performed in different chambers without vacuum in between.
10 . The method of claim 9 , wherein the filling metal is in physical contact with the silicon layer.
11 . The method of claim 9 , wherein the forming silicon layer comprises depositing elemental silicon.
12 . The method of claim 9 , wherein the metal-containing layer has a p-type work function, and the metal-containing layer and the silicon layer collectively have an n-type work function.
13 . The method of claim 9 , wherein silicon in the gate stack has a peak silicon atomic percentage in the silicon layer, and wherein silicon atomic percentage in the metal-containing layer is lower than the peak silicon atomic percentage.
14 . A method comprising:
forming a first gate spacer and a second gate spacer over a semiconductor region;
forming a gate stack over the semiconductor region and between the first gate spacer and the second gate spacer, the forming the gate stack comprising:
depositing a high-k dielectric layer;
depositing a titanium nitride layer over and contacting the high-k dielectric layer;
depositing a silicon layer over and directly contacting the titanium nitride layer, wherein the silicon layer comprises elemental silicon therein, and the silicon layer forms a ring encircling the semiconductor region; and
depositing a filling metal region over and contacting the silicon layer; and
forming a source/drain region on a side of the gate stack, wherein the source/drain region is of n-type, and wherein the titanium nitride layer and the silicon layer in combination act as a work-function layer that has an n-type work-function.
15 . The method of claim 14 , wherein silicon has a peak silicon atomic percentage in the silicon layer, and wherein silicon atomic percentage reduces continuously into the filling metal region and the titanium nitride layer.
16 . The method of claim 9 , wherein the silicon layer comprises a compound comprising silicon and nitrogen.
17 . The method of claim 9 , wherein at a time the filling metal is formed, the silicon layer is free from silicon oxide therein.
18 . The method of claim 1 further comprising:
depositing an additional metal-containing layer over and contacting the silicon-containing layer; and
depositing an additional silicon-containing layer over and contacting the additional metal-containing layer, wherein the additional silicon-containing layer comprises elemental silicon.