Silicon intermixing layer for blocking diffusion

1. A method of forming an integrated circuit structure, the method comprising:

forming a gate dielectric on a substrate;

forming a work function layer over the gate dielectric;

depositing a capping layer comprising titanium nitride over the work function layer, wherein the depositing the capping layer is performed starting with a first TiCl 4 pulsing and purging cycle, followed by a NH 3 pulsing and purging cycle, wherein the depositing the capping layer is ended with a second TiCl 4 pulsing and purging cycle, and wherein the second TiCl 4 pulsing and purging cycle is performed at an elevated wafer temperature, and is free from plasma;

soaking the capping layer in a silicon-containing gas to form a silicon-containing layer;

after the silicon-containing layer is formed, performing a vacuum break to expose the silicon-containing layer to air and to form a silicon-and-oxygen-containing layer;

forming a blocking layer over the silicon-and-oxygen-containing layer; and

forming a metal-filling region over the blocking layer.

2. The method of claim 1 , wherein the depositing the capping layer comprises a plurality of cycles, each comprising:

a TiCl 4 cycle comprising pulsing and purging TiCl 4 ; and

an NH 3 cycle comprising pulsing and purging NH 3 , wherein the second TiCl 4 pulsing and purging cycle is performed after a last cycle of the plurality of cycles.

3. The method of claim 1 , wherein in the soaking the capping layer, the capping layer is soaked in the silicon-containing gas comprising a gas selected from the group consisting of SiH 4 , Si 2 H 6 , Dichlorosilane (DCS), and combinations thereof.

4. The method of claim 1 , wherein in the soaking the capping layer, the substrate is heated to a temperature in a range between about 400° C. and about 600° C.

5. The method of claim 1 , wherein the forming the work function layer, the depositing the capping layer, and the soaking the capping layer are in-situ performed in a same vacuum environment.

6. The method of claim 5 , wherein the depositing the capping layer and the soaking the capping layer are performed in a same process chamber.

7. The method of claim 1 further comprising:

forming a dummy gate stack on a sidewall and a top surface of a semiconductor fin;

forming gate spacers on opposite sides of the dummy gate stack;

forming an inter-layer dielectric, with the dummy gate stack and the gate spacers being in the inter-layer dielectric; and

removing the dummy gate stack to form a trench between the gate spacers, wherein the gate dielectric and the work function layer are formed to extend into the trench.

8. The method of claim 1 , wherein the NH 3 pulsing and purging cycle that is immediately preceding the second TiCl 4 pulsing and purging cycle results a layer of titanium nitride to be deposited.

9. A method comprising:

forming a gate stack on a semiconductor region, the forming the gate stack comprising:

forming a gate dielectric;

depositing a work function layer over the gate dielectric;

depositing a first titanium nitride layer over the work function layer, wherein the depositing the first titanium nitride layer is performed starting with a first TiCl 4 pulsing and purging cycle, followed by a NH 3 pulsing and purging cycle, wherein the depositing the first titanium nitride layer is ended with a second TiCl 4 pulsing and purging cycle, and wherein the second TiCl 4 pulsing and purging cycle is performed at an elevated wafer temperature, and is free from plasma;

forming a silicon-containing layer over the first titanium nitride layer, wherein the forming the silicon-containing layer comprises a soaking process in a silicon-containing gas;

depositing a second titanium nitride layer over the silicon-containing layer; and

depositing a metal-filling region over the second titanium nitride layer.

10. The method of claim 9 , wherein the NH 3 pulsing and purging cycle that is immediately preceding the second TiCl 4 pulsing and purging cycle results a layer of titanium nitride to be deposited.

11. The method of claim 10 , wherein the silicon-containing layer is deposited using atomic layer deposition.

12. The method of claim 9 , wherein the silicon-containing gas is selected from the group consisting of SiH 4 , Si 2 H 6 , Dichlorosilane (DCS), and combinations thereof.

13. The method of claim 9 , wherein the silicon-containing layer has a thickness in a range between about 0.1 nm and about 1.5 nm.

14. The method of claim 9 , wherein the soaking process is performed in the silicon-containing gas selected from the group consisting of SiH 4 , Si 2 H 6 , Dichlorosilane (DCS), and combinations thereof.

15. A method of forming an integrated circuit structure, the method comprising:

forming a gate dielectric on a semiconductor region;

forming a work function layer over the gate dielectric;

depositing a first titanium nitride layer over the work function layer, wherein the depositing the first titanium nitride layer is performed starting with a first TiCl 4 pulsing and purging cycle, followed by a NH 3 pulsing and purging cycle, wherein the depositing the first titanium nitride layer is ended with a second TiCl 4 pulsing and purging cycle, and wherein the second TiCl 4 pulsing and purging cycle is performed at an elevated wafer temperature, and is free from plasma;

soaking the first titanium nitride layer in a silicon-containing gas to form a silicon-containing layer;

exposing the silicon-containing layer to oxygen to convert a portion of the silicon-containing layer into a silicon oxide containing layer, wherein the exposing the silicon-containing layer to oxygen is performed at a room temperature;

forming a second titanium nitride layer over the silicon oxide containing layer; and

forming a metal-filling region over the second titanium nitride layer.

16. The method of claim 15 , wherein the depositing the first titanium nitride layer comprises a plurality of processes comprising pulsing TiCl 4 , purging TiCl 4 , pulsing NH 3 , and purging NH 3 .

17. The method of claim 15 , wherein the second TiCl 4 pulsing and purging cycle is performed at the elevated wafer temperature in a range between about 400° C. and about 600° C.

18. The method of claim 15 , wherein the exposing the silicon-containing layer to oxygen comprises exposing the silicon-containing layer to air.

19. The method of claim 15 , wherein the silicon-containing gas is selected from the group consisting of SiH 4 , Si 2 H 6 , Dichlorosilane (DCS), and combinations thereof.