IP Library › Granted Patent US 11,881,771

Granted Patent B2

US 11,881,771 · App. 17/649,655 · Granted Jan 23, 2024

Half-bridge power circuit, controller therefor, and method for controlling the same

Inventors: Bo Fan (Tianjin, CN); Meng Wang (Tanggu, CN); Pengcheng Lin (Tianjin, CN)

Assignee: NXP USA, INC.

H02M3/155 G05F1/613 H02M1/08 H02M7/219 H02M3/156 H02M3/158 H02M3/1588

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Quick Facts

Patent No.: US 11,881,771
App. No.: 17/649,655
Granted: Jan 23, 2024
Kind: B2

External Links

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Abstract

A controller for a half-bridge power circuit includes a measurement circuit, a controller circuit, a high-side delay circuit, and a low-side delay circuit. The measurement circuit connects to the half-bridge node, measures the half-bridge voltage, and generates a multi-bit status signal indicative of the measured half-bridge voltage. The controller circuit connects to the measurement circuit, and receives the status signal therefrom. The controller circuit generates at least a delay control signal based on the status signal. The high-side delay circuit connects to the controller circuit to receive the delay control signal. The high-side delay circuit provides a high-side control signal in response to the delay control signal, to switch on/off the high-side switch. The low-side delay circuit connects to the controller circuit to receive the delay control signal. The low-side delay circuit provides a low-side control signal in response to the delay control signal, to switch on/off the low-side switch.

Claims (113)

1. A controller for a half-bridge power circuit comprising a high-side switch and a low-side switch, wherein the high-side switch and the low-side switch are series connected between a power supply and ground, and a half-bridge node between the high-side switch and the low-side switch provides a half-bridge voltage; wherein the controller comprises:

a measurement circuit configured to be connected to the half-bridge node, wherein the measurement circuit is configured to measure the half-bridge voltage, and generate a multi-bit status signal indicative of the measured half-bridge voltage;

a controller circuit connected to the measurement circuit and configured to receive the status signal therefrom, wherein the controller circuit is configured to generate at least a delay control signal based on the status signal and generate a rise deadtime setting signal as the delay control signal in response to the status signal;

a high-side delay circuit connected to the controller circuit to receive the delay control signal, wherein the high-side delay circuit is configured to provide a high-side control signal in response to the delay control signal, to switch on/off the high-side switch, wherein the high-side delay circuit comprises:

a high-side ON delay circuit configured to receive the rise deadtime setting signal from the controller circuit, and generate a high-side ON signal as a response;

a high-side buffer circuit configured to receive an inverted version of a PWM signal, and generate a high-side OFF signal in response to the inverted version of the PWM signal; and

a high-side trigger circuit connected to the high-side ON delay circuit and the high-side buffer circuit, and configured to generate the high-side control signal based on the high-side ON signal and the high-side OFF signal; and

a low-side delay circuit connected to the controller circuit to receive the delay control signal, wherein the low-side delay circuit is configured to provide a low-side control signal in response to the delay control signal, to switch on/off the low-side switch.

2. The controller of claim 1 , further comprising a high-side driver circuit connected to the high-side delay circuit to receive the high-side control signal, wherein

the high-side driver circuit is configured to generate a high-side driver signal in response to the high-side control signal, and provide the high-side driver signal to control the high-side switch; and wherein

the controller circuit is further configured to generate a high-side slew-rate control signal in response to the status signal; and

the high-side driver circuit is further connected to the controller circuit to receive the high-side slew-rate control signal, and wherein the high-side driver signal is generated dependent on the high-side slew-rate control signal.

3. The controller of claim 1 , wherein the low-side delay circuit comprises:

a low-side OFF delay circuit configured to receive the rise deadtime setting signal from the controller circuit, and generate a low-side OFF signal as a response;

a low-side ON delay circuit configured to receive the inverted version of the PWM signal, and generate a low-side ON signal in response to the inverted version of the PWM signal; and

a low-side trigger circuit connected to the low-side OFF delay circuit and the low-side ON delay circuit, and configured to generate the low-side control signal based on the low-side OFF signal and the low-side ON signal;

wherein the controller further comprises a low-side driver circuit connected to the low-side delay circuit to receive the low-side control signal, wherein the low-side driver circuit is configured to generate a low-side driver signal in response to the low-side control signal, and provide the low-side driver signal to control the low-side switch.

4. The controller of claim 1 , wherein the controller circuit is configured to generate a fall deadtime setting signal as the delay control signal in response to the status signal, and wherein the low-side delay circuit comprises:

a low-side ON delay circuit configured to receive the fall deadtime setting signal from the controller circuit, and generate a low-side ON signal as a response;

a low-side buffer circuit configured to receive a PWM signal, and generate a low-side OFF signal in response to the PWM signal; and

a low-side trigger circuit connected to the low-side ON delay circuit and the low-side buffer circuit, and configured to generate the low-side control signal based on the low-side ON signal and the low-side OFF signal.

5. The controller of claim 4 , further comprising a low-side driver circuit connected to the low-side delay circuit to receive the low-side control signal, wherein

the low-side driver circuit is configured to generate a low-side driver signal in response to the low-side control signal, and provide the low-side driver signal to the low-side switch; and wherein

the controller circuit is further configured to generate a low-side slew-rate control signal in response to the status signal; and

the low-side driver circuit is further connected to the controller circuit to receive the low-side slew-rate control signal, and wherein the low-side driver signal is generated dependent on the low-side slew-rate control signal.

6. The controller of claim 4 , wherein the high-side delay circuit comprises:

a high-side OFF delay circuit configured to receive the fall deadtime setting signal from the controller circuit, and generate a high-side OFF signal as a response;

a high-side ON delay circuit configured to receive the PWM signal, and generate a high-side ON signal in response to the PWM signal; and

a high-side trigger circuit connected to the high-side OFF delay circuit and the high-side ON delay circuit, and configured to generate the high-side control signal based on the high-side OFF signal and the high-side ON signal;

and wherein the controller further comprises a high-side driver circuit connected to the high-side delay circuit to receive the high-side control signal, wherein the high-side driver circuit is configured to generate a high-side driver signal in response to the high-side control signal, and provide the high-side driver signal to the high-side switch.

7. The controller of claim 1 , wherein the controller circuit is configured to generate a rise deadtime setting signal in response to a first status signal, and a fall deadtime setting signal in response to a second status signal, and wherein the high-side delay circuit comprises:

a high-side ON delay circuit configured to receive the fall deadtime setting signal from the controller circuit and a PWM signal, and generate a high-side ON signal as a response;

a high-side OFF delay circuit configured to receive the rise deadtime setting signal from the controller circuit and an inverted version of the PWM signal, and generate a high-side OFF signal as a response; and

a high-side trigger circuit connected to the high-side ON delay circuit and the high-side OFF delay circuit, and configured to generate the high-side control signal based on the high-side ON signal and the high-side OFF signal.

8. The controller of claim 7 , further comprising a high-side driver circuit connected to the high-side delay circuit to receive the high-side control signal; wherein

the controller circuit is further configured to generate a high-side slew-rate control signal in response to the status signal, and provide the high-side slew-rate control signal to the high-side driver circuit; and wherein

the high-side driver circuit is configured to generate a high-side driver signal dependent on the high-side control signal and the high-side slew-rate control signal, and provide the high-side driver signal to the high-side switch.

9. The controller of claim 1 , wherein the controller circuit is configured to generate a rise deadtime setting signal in response to a first status signal, and a fall deadtime setting signal in response to a second status signal, and wherein the low-side delay circuit comprises:

a low-side ON delay circuit configured to receive the rise deadtime setting signal from the controller circuit and an inverted version of a PWM signal, and generate a low-side ON signal as a response;

a low-side OFF delay circuit configured to receive the fall deadtime setting signal from the controller circuit and the PWM signal, and generate a low-side OFF signal as a response; and

a low-side trigger circuit connected to the low-side ON delay circuit and the low-side OFF delay circuit, and configured to generate the low-side control signal based on the low-side ON signal and the low-side OFF signal.

10. The controller of claim 9 , further comprising a low-side driver circuit connected to the low-side delay circuit to receive the low-side control signal; wherein

the controller circuit is further configured to generate a low-side slew-rate control signal in response to the status signal, and provide the low-side slew-rate control signal to the low-side driver circuit; and wherein

the low-side driver circuit is configured to generate a low-side driver signal dependent on the low-side control signal and the low-side slew-rate control signal, and provide the low-side driver signal to the low-side switch.

11. The controller of claim 1 , wherein the high-side delay circuit is configured to provide the high-side control signal to apply a delay in switching on/off the high-side switch, and the low-side delay circuit is configured to provide the low-side control signal to apply a delay in switching on/off the low-side switch, wherein during a rising phase of the half-bridge voltage:

the high-side delay circuit is configured to provide the high-side control signal to

reduce a delay in switching on the high-side switch in response to the status signal indicating the half-bridge voltage is measured as lower than a first lower limit voltage; and

add a delay in switching on the high-side switch in response to the status signal indicating the half-bridge voltage is measured as higher than a first higher limit voltage;

and the low-side delay circuit is configured to provide the low-side control signal to

add a delay in switching off the low-side switch in response to the status signal indicating the half-bridge voltage is measured as lower than the first lower limit voltage; and

reduce a delay in switching off the low-side switch in response to the status signal indicating the half-bridge voltage is measured as lower than the first higher limit voltage.

12. The controller of claim 1 , wherein the high-side delay circuit is configured to provide a high-side control signal to apply a delay in switching on/off the high-side switch, and the low-side delay circuit is configured to provide a low-side control signal to apply a delay in switching on/off the low-side switch, wherein during a falling phase of the half-bridge voltage:

the low-side delay circuit is configured to provide the low-side control signal to

reduce a delay in switching on the low-side switch in response to the status signal indicating the half-bridge voltage is measured as higher than a second higher limit voltage; and

add a delay in switching on the low-side switch in response to the status signal indicating the half-bridge voltage is measured as lower than a second lower limit voltage;

and the high-side delay circuit is configured to provide the high-side control signal to

add a delay in switching off the high-side switch in response to the status signal indicating the half-bridge voltage is measured as higher than the second higher limit voltage; and

reduce a delay in switching off the high-side switch in response to the status signal indicating the half-bridge voltage is measured as lower than the second lower limit voltage.

13. A method of operating a half-bridge power circuit, wherein the half-bridge power circuit comprises a high-side switch connected between a power supply and a half-bridge node, and a low-side switch connected between the high-side switch and ground; wherein the method comprises:

a measurement circuit connected to the half-bridge node and measuring a half-bridge voltage at the half-bridge node, and generating a multi-bit status signal indicative of the measured half-bridge voltage, wherein generating a multi-bit status signal comprises:

the measurement circuit comparing the half-bridge voltage with a first reference voltage, and generating a first bit of the status signal indicative of whether the half-bridge voltage is higher than the first reference voltage;

the measurement circuit comparing the half-bridge voltage with at least a second reference voltage, and generating a second bit of the status signal indicative of whether the half-bridge voltage is higher than the second reference voltage; and

the measurement circuit providing the first bit and at least the second bit as the status signal;

a controller circuit connected to the measurement circuit and generating at least a delay control signal based on the status signal;

a high-side delay circuit connected to the controller circuit and generating a high-side control signal using the delay control signal, wherein the high-side switch is switched on/off depending on the high-side control signal;

a low-side delay circuit connected to the controller circuit and generating a low-side control signal using the delay control signal, wherein the low-side switch is switched on/off depending on the low-side control signal; and

the half-bridge node providing the half-bridge voltage of the half-bridge power circuit.

14. The method of claim 13 , further comprising:

during a rising phase of the half-bridge voltage, the controller circuit comparing a value of the multi-bit status signal with a first lower limit value corresponding to a first lower limit voltage, to determine whether the half-bridge voltage is lower than the first lower limit voltage; and

the high-side delay circuit generating the high-side control signal using the delay control signal to reduce a predetermined delay time from a current first delay time in response to the half-bridge voltage being lower than the first lower limit voltage;

wherein the method further comprises: the high-side switch being on in response to the high-side control signal by applying the first delay time;

and wherein the method further comprises:

during the rising phase of the half-bridge voltage, the low-side delay circuit generating the low-side control signal using the delay control signal to add a predetermined delay time into a current second delay time in response to the half-bridge voltage being lower than the first lower limit voltage; and

the low-side switch being off in response to the low-side control signal by applying the second delay time.

15. The method of claim 14 , further comprising:

during the rising phase of the half-bridge voltage, the controller circuit comparing a value of the multi-bit status signal with a first upper limit value corresponding to a first upper limit voltage, to determine whether the half-bridge voltage is higher than the first upper limit voltage; and

the high-side delay circuit generating the high-side control signal using the delay control signal to add a predetermined delay time into the current first delay time in response to the half-bridge voltage being higher than the first upper limit voltage;

and wherein the method further comprises:

during the rising phase of the half-bridge voltage, the low-side delay circuit generating the low-side control signal using the delay control signal to reduce a predetermined delay time from a current second delay time in response to the half-bridge voltage being higher than the first upper limit voltage.

16. The method of claim 13 , further comprising:

during a falling phase of the half-bridge voltage, the controller circuit comparing a value of the multi-bit status signal with a second higher limit value corresponding to a second upper limit voltage, to determine whether the half-bridge voltage is higher than the second upper limit voltage; and

the low-side delay circuit generating the low-side control signal using the delay control signal to reduce a predetermined delay time from a current third delay time in response to the half-bridge voltage being higher than the second upper limit voltage;

wherein the method further comprises: the low-side switch being on in response to the low-side control signal by applying the third delay time;

and wherein the method further comprises:

during the falling phase of the half-bridge voltage, the high-side delay circuit generating the high-side control signal using the delay control signal to add a predetermined delay time into a current fourth delay time in response to the half-bridge voltage being higher than the second upper limit voltage; and

the high-side switch being off in response to the high-side signal by applying the fourth delay time.

17. The method of claim 16 , further comprising:

during the falling phase of the half-bridge voltage, the controller circuit comparing a value of the multi-bit status signal with a second lower limit value corresponding to a second lower limit voltage, to determine whether the half-bridge voltage is lower than the second lower limit voltage; and

the low-side delay circuit generating the low-side control signal using the delay control signal to add a predetermined delay time into the current third delay time in response to the half-bridge voltage being lower than the second lower limit voltage;

and wherein the method further comprises:

during the falling phase of the half-bridge phase, the high-side delay circuit generating the high-side control signal using the delay control signal to reduce a predetermined delay time from a current fourth delay time in response to the half-bridge voltage being lower than the second lower limit voltage.

18. The method of claim 13 , further comprising:

the controller circuit generating, in response to the status signal, a high-side slew-rate control signal and a low-side slew-rate control signal;

the controller circuit providing the high-side slew-rate control signal to a high-side driver circuit;

the controller circuit providing the low-side slew-rate control signal to a low-side driver circuit;

the high-side driver circuit generating a high-side driver signal dependent on the high-side control signal and the high-side slew-rate control signal, and driving the high-side switch using the high-side driver signal; and

the low-side driver circuit generating a low-side driver signal dependent on the low-side control signal and the low-side slew rate control signal, and driving the low-side switch using the low-side driver signal.

19. A controller for a half-bridge power circuit comprising a high-side switch and a low-side switch, wherein the high-side switch and the low-side switch are series connected between a power supply and ground, and a half-bridge node between the high-side switch and the low-side switch provides a half-bridge voltage; wherein the controller comprises:

a controller circuit connected to the measurement circuit and configured to receive the status signal therefrom, wherein the controller circuit is configured to generate at least a delay control signal based on the status signal and generate a fall deadtime setting signal as the delay control signal in response to the status signal;

a low-side ON delay circuit configured to receive the fall deadtime setting signal from the controller circuit, and generate a low-side ON signal as a response;

a low-side buffer circuit configured to receive a PWM signal, and generate a low-side OFF signal in response to the PWM signal; and

20. A controller for a half-bridge power circuit comprising a high-side switch and a low-side switch, wherein the high-side switch and the low-side switch are series connected between a power supply and ground, and a half-bridge node between the high-side switch and the low-side switch provides a half-bridge voltage; wherein the controller comprises:

a controller circuit connected to the measurement circuit and configured to receive the status signal therefrom, wherein the controller circuit is configured to generate at least a delay control signal based on the status signal and generate a rise deadtime setting signal in response to a first status signal, and a fall deadtime setting signal in response to a second status signal;

a high-side ON delay circuit configured to receive the fall deadtime setting signal from the controller circuit and a PWM signal, and generate a high-side ON signal as a response;

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2022

From: FAN, BO; WANG, MENG; LIN, PENGCHENG

To: NXP USA, INC.

Reel/Frame 058954/0963 →

Priority Claims (1)

CN 202110176570.6 · Feb 9, 2021 · national

Continuity (1)

Related Publication 20220255424A1 · Aug 11, 2022

Cited By (2)

US 12,316,210 US 12,738,838