Process of forming an electronic device including a component structure adjacent to a trench
A process of forming an electronic device can form an accumulation channel or an integrated diode by selective doping parts of a workpiece. In an embodiment, a doped region can be formed by implanting a sidewall of a body region. In another embodiment, a doped region can correspond to a remaining portion of a semiconductor layer after forming another doped region by implanting into a contact opening. The accumulation channel or the integrated diode can lower the barrier for a body diode turn-on. Reduced stored charge and Q RR may be achieved, leading to lower switching losses.
1 . A process, comprising:
patterning a substrate to define a first trench, wherein the substrate includes a first doped region having a first conductivity type, wherein the first trench extends at least partly through the first doped region;
forming a second doped region within a first semiconductor pillar and along a sidewall of the first trench, wherein the second doped region has the first conductivity type, wherein the second doped region has a greater average dopant concentration as compared to the first doped region;
forming a third doped region within the first semiconductor pillar, wherein the third doped region has a second conductivity type opposite the first conductivity type;
forming a source region within the first semiconductor pillar and along the sidewall of the first trench, wherein the source region has the first conductivity type; and
forming a first contact to the third doped region,
wherein, in a finished electronic device:
the second doped region and the third doped region overlie the first doped region,
at least a part of the third doped region is spaced apart from the sidewall of the first trench by the second doped region,
the second doped region lies along a current path between the first doped region and the first contact, and
the source region extends a first distance from the sidewall of the first trench, the second doped region extends a second distance from the sidewall of the first trench, and the first distance is greater than the second distance.
2 . The process of claim 1 , further comprising:
forming an insulating layer along the sidewall and a bottom of the first trench; and
forming a shield electrode within the first trench, wherein the insulating layer is disposed between the substrate and the shield electrode.
3 . The process of claim 2 , wherein forming the insulating layer and forming the shield electrode are performed before forming the second doped region.
4 . The process of claim 1 , further comprising:
forming a dielectric layer along the sidewall of the first trench before forming the second doped region; and
forming a first electrode within the first trench after forming the second doped region.
5 . The process of claim 4 , wherein, in the finished electronic device, the second doped region, the third doped region, the dielectric layer, and the first electrode are parts of a component structure.
6 . The process of claim 5 , wherein:
patterning the substrate comprises patterning the substrate to define a second trench, wherein the second trench has a sidewall and extends at least partly through the first doped region,
during forming the second doped region, substantially no dopant is introduced into a second semiconductor pillar that is immediately adjacent to the second trench,
the process further comprises:
forming a gate dielectric layer along the sidewall of the second trench;
forming a gate electrode within the second trench, wherein the gate dielectric layer is disposed between the gate electrode and the sidewall of the second trench;
forming a body region that overlies the first doped region and is along the sidewall of the second trench;
forming a current-carrying region adjacent to the second trench; and
forming a second contact to the body region and the current-carrying region, and in the finished electronic device,
the body region extends to the sidewall of the second trench, and
the body region, the gate dielectric layer, the gate electrode, and the current-carrying region are parts of a transistor structure.
7 . The process of claim 6 , further comprising:
forming a first insulating layer along the sidewall and a bottom of the first trench and along the sidewall and a bottom of the second trench;
forming a first shield electrode within the first trench and forming a second shield electrode within the second trench; and
forming a second insulating layer over the first shield electrode and forming a third insulating layer over the second shield electrode, wherein forming the second insulating layer and forming the third insulating layer are performed before forming the dielectric layer,
wherein, in the finished electronic device:
the first contact, the second contact, the first shield electrode, the second shield electrode, and the current-carrying region are electrically connected to one another,
the component structure is at least part of a component,
the transistor structure is at least part of a power transistor, and
an area occupied by the component is in a range from 5% to 30% of a combined area occupied by the component and the power transistor.
8 . The process of claim 6 , wherein:
the component structure is at least part of a component,
the transistor structure is at least part of a transistor, and
an area occupied by the component is in a range from 5% to 30% of a combined area occupied by the component and the transistor.
9 . The process of claim 5 , further comprising:
forming a current-carrying region that overlies the third doped region and contacts the second doped region;
forming a first contact opening extending into the third doped region; and
forming a doped contact region within the third doped region and along a surface of the first contact opening,
wherein forming the first contact is performed such that an ohmic contact is formed to the third doped region and the current-carrying region.
10 . The process of claim 4 , wherein, in the finished electronic device, a Schottky contact is made to the second doped region.
11 . The process of claim 10 , wherein forming the second doped region is performed, such that in the finished electronic device, the third doped region has an average dopant concentration in a range from 1×10 16 atoms/cm 3 to 9×10 17 atoms/cm 3 .
12 . The process of claim 1 , wherein the second doped region is discontinuous along the sidewall of the first trench.
13 . The process of claim 1 , wherein forming the second doped region is performed using a tilt angle implant.
14 . A process, comprising:
patterning a substrate to define a first trench, wherein the substrate includes a first doped region having a first conductivity type, wherein the first trench extends at least partly through the first doped region;
forming a second doped region within a first semiconductor pillar and along a sidewall of the first trench, wherein the second doped region has the first conductivity type;
forming a third doped region within the first semiconductor pillar, wherein the third doped region has a second conductivity type opposite the first conductivity type; and
forming a first contact to the second doped region and the third doped region, wherein the first contact is a Schottky contact to the second doped region and the third doped region,
wherein, in a finished electronic device:
the second doped region and the third doped region overlie the first doped region,
at least a part of the third doped region is spaced apart from the sidewall of the first trench by the second doped region,
the second doped region lies along a current path between the first doped region and the first contact, and
the second doped region, the third doped region, and the first contact are parts of a component structure, and the component structure does not include a source region.
15 . The process of claim 14 , wherein forming the second doped region is performed after patterning the substrate and comprises doping a portion of the first semiconductor pillar along the sidewall of the first trench.
16 . The process of claim 15 , wherein doping the portion of the first semiconductor pillar is performed using a tilt angle implant.
17 . The process of claim 14 , further comprising:
forming a dielectric layer along the sidewall of the first trench before forming the second doped region; and
forming a first electrode within the first trench after forming the second doped region.
18 . A process, comprising:
patterning a substrate to define a first trench, wherein the substrate includes a primary surface and a first doped region having a first conductivity type, wherein the first trench extends at least partly through the first doped region;
forming a second doped region within a first semiconductor pillar and along a sidewall of the first trench, wherein the second doped region has the first conductivity type, wherein the second doped region has a greater average dopant concentration as compared to the first doped region;
forming a third doped region within the first semiconductor pillar, wherein the third doped region has a second conductivity type opposite the first conductivity type; and
forming a first contact to the third doped region,
wherein, in a finished electronic device:
the second doped region and the third doped region overlie the first doped region,
the second doped region extends into in the first semiconductor pillar to a deeper depth as compared to the third doped region, wherein depth is measured in a direction perpendicular to the primary surface,
at least a part of the third doped region is spaced apart from the sidewall of the first trench by the second doped region, and
the second doped region lies along a current path between the first doped region and the first contact.
19 . A process, comprising:
patterning a substrate to define a first trench, wherein:
the substrate includes a first doped region having a first conductivity type,
the first trench extends at least partly through the first doped region, and
a first semiconductor pillar and a second semiconductor pillar are spaced apart from each other at least by the first trench;
forming a first body region within the first semiconductor pillar, wherein the first body region has a second conductivity type opposite the first conductivity type;
forming a second body region within the second semiconductor pillar, where the second body region has the second conductivity type;
forming a resist member over the second semiconductor pillar and not over the first semiconductor pillar;
forming a second doped region within a first semiconductor pillar and along a sidewall of the first trench, wherein forming the second doped region has the first conductivity type and is performed while the resist member overlies the second semiconductor pillar;
forming a first source region within the first semiconductor pillar, wherein the first source region has the first conductivity type;
forming a second source region within the second semiconductor pillar, wherein the second source region has the first conductivity type;
forming a first body contact region within a first portion of the first body region; and
forming a second body contact region within a second portion of the second body region;
wherein, in a finished electronic device:
the first body region has a first average dopant concentration that is different from a second average dopant concentration of the second body region, and
the second doped region lies along a current path between the first doped region and the first source region.
20 . The process of claim 19 , wherein, in the finished electronic device:
the first body region, the second doped region, the first source region, and the first body contact region are parts of a component structure,
the component structure is at least part of a component,
the second body region, the second source region, and the second body contact region are parts of a transistor structure,
the transistor structure is at least part of a transistor, and
an area occupied by the component is in a range from 5% to 30% of a combined area occupied by the component and the transistor.