Field effect transistor with gated and non-gated trenches
A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.
1. A field effect transistor (FET), comprising:
a gated trench disposed in a semiconductor region of a first conductivity type;
a non-gated trench disposed in the semiconductor region;
a body region of a second conductivity type disposed in the semiconductor region and adjacent the non-gated trench;
a first shield electrode disposed in a bottom portion of the gated trench;
a second shield electrode disposed in a bottom portion of the non-gated trench;
a dielectric layer disposed in the non-gated trench; and
a conductive material of the second conductivity type disposed in the non-gated trench such that the dielectric layer is disposed between the second shield electrode disposed in the non-gated trench and the conductive material, the conductive material contacting the body region adjacent the non-gated trench and contacting a sidewall of the non-gated trench.
2. The FET of claim 1 further comprising:
a source region of the first conductivity type disposed in the body region of the second conductivity type,
the conductive material disposed in the non-gated trench and contacting the source region; and
a source interconnect layer contacting the source region and the conductive material.
3. The FET of claim 2 wherein the source region extends across an entire width of a mesa region bounded along a lateral dimension by the gated trench and the non-gated trench.
4. The FET of claim 2 wherein the first shield electrode and the second shield electrode are electrically connected to the source interconnect layer.
5. The FET of claim 1 further comprising:
a shield dielectric layer lining a lower sidewall and a bottom surface of the gated trench;
an inter-electrode dielectric layer extending over the first shield electrode disposed in the gated trench; and
a gate electrode disposed over the inter-electrode dielectric layer in the gated trench.
6. The FET of claim 1 , wherein the conductive material disposed in the non-gated trench extends to a depth shallower than a depth of the body region adjacent the non-gated trench.
7. The FET of claim 1 , wherein the semiconductor region includes a highly doped substrate and an overlying epitaxial layer, the body region is formed in an upper portion of the overlying epitaxial layer, and the gated trench and the non-gated trench each terminate in the highly doped substrate.
8. The FET of claim 1 , wherein the semiconductor region includes a highly doped substrate and an overlying epitaxial layer, the body region is formed in an upper portion of the overlying epitaxial layer, and the gated trench and the non-gated trench each terminate in the overlying epitaxial layer.
9. The FET of claim 1 , wherein the conductive material disposed in the non-gated trench includes a polysilicon layer of the second conductivity type.
10. A field effect transistor (FET) comprising:
a gated trench disposed in a semiconductor region of a first conductivity type;
a non-gated trench disposed in the semiconductor region of the first conductivity type;
a body region of a second conductivity type disposed in the semiconductor region adjacent the non-gated trench;
a first shield electrode disposed in a bottom portion of the gated trench;
a second shield electrode disposed in a bottom portion of the non-gated trench, the second shield electrode disposed in the non-gated trench having a top surface at a height in the semiconductor region above a height of a bottom surface of the body region; and
a conductive material of the second conductivity type disposed in the non-gated trench such that the conductive material contacts the body region along a sidewall of the non-gated trench.
11. The FET of claim 10 , wherein the conductive material is in contact with the second shield electrode disposed in the non-gated trench.
12. The FET of claim 10 further comprising:
a source region of the first conductivity type disposed in the body region,
the conductive material disposed in the non-gated trench and contacting the source region; and
a source interconnect layer contacting the source region and the conductive material disposed in the non-gated trench.
13. The FET of claim 12 , wherein the source region extends across an entire width of a mesa region bounded along a lateral dimension by the gated trench and the non-gated trench.
14. The FET of claim 13 , wherein the first shield electrode disposed in the gated trench and the second shield electrode disposed in non-gated trench are electrically connected to the source interconnect layer.
15. The FET of claim 10 further comprising:
a shield dielectric layer lining a lower sidewall and a bottom surface of the gated trench;
a gate dielectric layer lining an upper sidewall of the gated trench and extending over the shield electrode in the gated trench; and
a gate electrode disposed over the gate dielectric layer in the gated trench.
16. The FET of claim 10 , wherein the conductive material disposed in the non-gated trench extends to a depth shallower than a depth of the body region adjacent the non-gated trench.
17. A field effect transistor (FET) comprising:
a gated trench disposed in a semiconductor region of a first conductivity type;
a plurality of non-gated trenches disposed in the semiconductor region of the first conductivity type;
a first shield electrode disposed in a bottom portion of the gated trench and a second shield electrode disposed in a bottom portion of at least one non-gated trench from the plurality of non-gated trenches; and
a dielectric layer disposed over the second shield electrode disposed in the non-gated trench; and
a body region of a second conductivity type disposed in the semiconductor region between a pair of non-gated trenches from the plurality of non-gated trenches; and
a heavy body region disposed in the body region, the heavy body region being adjacent a sidewall of at least one non-gated trench of the pair of non-gated trenches.
18. The FET of claim 17 further comprising:
a source region of the first conductivity type disposed in the body region; and
a source interconnect layer contacting an upper surface of the source region, the source interconnect layer disposed in an upper portion of the at least one non-gated trench and in contact with the source region and the heavy body region along an upper sidewall of the at least one non-gated trench.
19. The FET of claim 17 , wherein the semiconductor region includes a highly doped substrate and an overlying epitaxial layer, the body region is formed in an upper portion of the overlying epitaxial layer, and the gated trench and the non-gated trench each terminate in the overlying epitaxial layer.
20. The FET of claim 17 , wherein the semiconductor region includes a highly doped substrate and an overlying epitaxial layer, the body region is formed in an upper portion of the overlying epitaxial layer, and the gated trench and the non-gated trench each terminate in the highly doped substrate.
21. The FET of claim 17 , wherein the gated trench is a first gated trench, the pair of the non-gated trenches is formed between the first gated trench and a second gated trench.