Self-aligned contact (SAC) in nanosheet transistors
Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet and a dielectric nanosheet as a top layer of the nanosheet stack is provided above a semiconductor substrate. A dummy gate with a gate cap and spacers on the sidewalls straddle over the nanosheet stack. End portions of the sacrificial semiconductor material nanosheets are recessed. A dielectric spacer material layer is formed. A source/drain region is formed on the sidewalls of each semiconductor channel material nanosheet. The dummy gate and gate cap are removed. Each sacrificial semiconductor material nanosheet is removed. A functional gate structure is formed that wraps around each suspended semiconductor channel material nanosheet. A self-aligned source/drain contact region is formed. A gate contact region is formed in a trench in the semiconductor substrate.
1 . A semiconductor structure comprising:
a plurality of stacked and suspended semiconductor channel material nanosheets located above a semiconductor substrate;
a functional gate structure surrounding a portion of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets;
a dielectric nanosheet on top of and covering a top surface of the functional gate structure, wherein: with respect to the functional gate structure, the dielectric nanosheet directly contacts only a gate dielectric portion of the functional gate structure;
a source/drain region on each side of the functional gate structure and physically contacting sidewalls of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets;
a self-aligned contact region directly contacting: (i) a sidewall of the dielectric nanosheet, (ii) a sidewall of a second dielectric nanosheet, and (iii) a portion of each source/drain region, wherein the second dielectric nanosheet is covering a top surface of a second functional gate structure surrounding a portion of each semiconductor channel material nanosheet of a second plurality of stacked and suspended semiconductor channel material nanosheets; and
a gate contact contacting a portion of the functional gate structure, the gate contact passing through the semiconductor substrate.
2 . The semiconductor structure of claim 1 , further comprising an isolation layer on the semiconductor substrate and beneath the functional gate structure.
3 . The semiconductor structure of claim 1 , further comprising a dielectric spacer on sidewalls of the gate contact.
4 . The semiconductor structure of claim 1 , wherein each of the plurality of stacked and suspended semiconductor channel material nanosheets comprises at least three nanosheets.
5 . The semiconductor structure of claim 1 , further comprising an interlevel dielectric (ILD) material with a top surface coplanar with a top surface of the self-aligned contact region.
6 . The semiconductor structure of claim 1 , further comprising inner spacers contacting sidewalls of the functional gate structure and located on an outer portion of each semiconductor material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets.
7 . The semiconductor structure of claim 1 , wherein the sidewalls of each semiconductor channel material nanosheet of the plurality of stacked and suspended semiconductor channel material nanosheets are vertically aligned to one another.
8 . The semiconductor structure of claim 1 , wherein each functional gate structure comprises (i) the gate dielectric portion physically contacting the semiconductor channel material nanosheet and (ii) a gate conductor portion physically contacting the gate dielectric portion.
9 . The semiconductor structure of claim 1 , wherein the semiconductor substrate and each semiconductor channel material nanosheet is composed of a same semiconductor material.
10 . The semiconductor structure of claim 2 , further comprising a region that includes a shallow trench isolation (STI) material that is physically contacting the semiconductor substrate and the isolation layer.
11 . A method for forming a semiconductor structure, the method comprising:
providing a nanosheet stack of (i) alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet and (ii) a dielectric nanosheet as a top layer of the nanosheet stack, the nanosheet stack located above a semiconductor substrate, wherein a dummy gate with a gate cap and spacers on sidewalls of the dummy gate and the gate cap straddle over the nanosheet stack;
recessing end portions of each of the sacrificial semiconductor material nanosheets to provide a gap between each of the semiconductor channel material nanosheets;
forming a dielectric spacer material layer within each gap;
forming a source/drain region by epitaxial growth of a semiconductor material on physically exposed sidewalls of each semiconductor channel material nanosheet;
removing the dummy gate and the gate cap;
removing each sacrificial semiconductor material nanosheet to suspend each semiconductor channel material nanosheet and the dielectric nanosheet;
forming a functional gate structure in regions occupied by each sacrificial semiconductor material nanosheet, wherein:
the functional gate structure wraps around each suspended semiconductor channel material nanosheet; and
with respect to the functional gate structure, the dielectric nanosheet directly contacts only a gate dielectric portion of the functional gate structure;
forming a self-aligned contact region, wherein the self-aligned contact region directly contacts: (i) a sidewall of the dielectric nanosheet, (ii) a sidewall of a second dielectric nanosheet, and (iii) the source/drain region and is laterally adjacent to the spacers and the dielectric nanosheet, wherein the second dielectric nanosheet is covering a top surface of a second functional gate structure surrounding a portion of each semiconductor channel material nanosheet of a second plurality of stacked and suspended semiconductor channel material nanosheets; and
forming a gate contact region in a trench in the semiconductor substrate, the gate contact region contacting the functional gate structure.
12 . The method of claim 11 , further comprising:
providing a bottom sacrificial semiconductor material layer on the semiconductor substrate; and
subsequent to providing the nanosheet stack:
removing the bottom sacrificial semiconductor material layer; and
forming an isolation layer on the semiconductor substrate.
13 . The method of claim 11 , further comprising:
forming interlevel dielectric (ILD) material above the source/drain region and above an adjacent region.
14 . The method of claim 11 , wherein forming the functional gate structure comprises:
additionally forming the functional gate structure in regions occupied by the dummy gate and the gate cap; and
recessing a gate conductor portion of the functional gate structure to expose the dielectric nanosheet.
15 . The method of claim 14 , further comprising:
subsequent to recessing the gate conductor portion of the functional gate structure, forming a dielectric cap in the regions occupied by the dummy gate and the gate cap.
16 . The method of claim 13 , further comprising:
prior to forming the self-aligned contact region, forming additional interlevel dielectric (ILD) material on the ILD material and the spacers, wherein the self-aligned contact region passes through a trench passing through the ILD material and the additional ILD material.
17 . The method of claim 11 , wherein forming the gate contact region in the trench in the semiconductor substrate comprises:
flipping a wafer containing the semiconductor structure;
forming the trench in the semiconductor substrate; and
forming the gate contact region in the trench in the semiconductor substrate, the gate contact region contacting the functional gate structure.
18 . The method of claim 17 , further comprising:
prior to forming the gate contact region in the trench in the semiconductor substrate, forming a gate spacer on sidewalls of the trench in the semiconductor substrate.
19 . The method of claim 17 , further comprising:
prior to forming the trench in the semiconductor substrate, recessing the semiconductor substrate.
20 . The semiconductor structure of claim 1 , wherein a top surface of the dielectric nanosheet is above a top surface of the functional gate structure.