IP Library Granted Patent US 12,469,701
Granted Patent B2
US 12,469,701 · App. 17/658,538 · Granted Nov 11, 2025

Patterning features with metal based resists

Inventors: Katie Lutker-Lee (Albany, NY); Angelique Raley (Albany, NY)
Assignee: Tokyo Electron Limited
H01L21/0337H01L21/0276H01L21/0332H01L21/0338H01L21/31116H01L21/31122H01L21/31138H01L21/31144H01L21/32136H01L21/32137H01L21/32139
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Quick Facts
Patent No.
US 12,469,701
App. No.
17/658,538
Granted
Nov 11, 2025
Kind
B2
Abstract

A method of forming a semiconductor device includes receiving a substrate in a plasma chamber, the substrate comprising an EUV patterned first mask material comprising a metal-based resist (MBR) and an underlying layer disposed between the substrate and the first mask material; depositing, selectively, a second mask material on the first masking layer using a first plasma comprising a source gas that reacts selectively with the first masking layer relative to the underlying layer; and etching the portion of the underlying layer to form a patterned underlying layer using the second masking layer and the first masking layer as an etch mask.

Claims (38)

1 . A method of forming a semiconductor device, the method comprising:

receiving a substrate in a plasma chamber, the substrate comprising a first masking layer comprising a metal-based resist (MBR) and an underlying layer disposed between a substrate layer and the first masking layer;

depositing selectively, a second masking layer on the first masking layer using a first plasma comprising a source gas that chemically and selectively reacts with the MBR relative to the underlying layer; and

etching a portion of the underlying layer to form a patterned underlying layer using the second masking layer and the first masking layer as an etch mask.

2 . The method of claim 1 , wherein the underlying layer comprises a silicon-based dielectric.

3 . The method of claim 1 , further comprising performing a trim etch process in the plasma chamber to remove a portion of the second masking layer.

4 . The method of claim 1 , wherein depositing the second masking layer comprises a thickness along a sidewall of the first masking layer which is less than a thickness of the second masking layer over a top surface of the first masking layer.

5 . The method of claim 1 , wherein the second masking layer comprises silicon or an organic polymer.

6 . The method of claim 1 , wherein the source gas comprises SiF 4 or CO.

7 . The method of claim 6 , wherein the first plasma further comprises an additive gas, the additive gas being H 2 , SiCl 4 , CH 4 , CH x F 4-x , or a mixture thereof and/or a diluent gas, the diluent gas being Ar, N 2 , or He.

8 . The method of claim 6 , wherein the first plasma further comprises an additive gas, the additive gas being H 2 , CH 4 , CH x F 4-x , CO 2 , O 2 , or a mixture thereof.

9 . The method of claim 1 , wherein the first masking layer has a first line edge roughness value and the second masking layer has a second line edge roughness value, wherein the first line edge roughness value is greater than the second line edge roughness value.

10 . A method of forming a semiconductor device, the method comprising:

depositing a layer of a first mask material comprising a metal-based resist (MBR), the layer covering an underlying layer of a substrate;

patterning the first mask material using an extreme ultraviolet (EUV) lithography process to form a first masking layer and expose a portion of the underlying layer; and

etching the underlying layer using a cyclic process comprising:

depositing a second masking layer selectively on the first masking layer by exposing the substrate to a first plasma, the first plasma comprising a source gas that chemically and selectively reacts with the MBR relative to the underlying layer; and

exposing the substrate to a second plasma.

11 . The method of claim 10 ,

wherein the second masking layer comprises silicon, and

wherein the first plasma comprises the source gas and a diluent gas, the source gas comprising SiF 4 and the diluent gas comprising Ar, N 2 , or He.

12 . The method of claim 10 ,

wherein the second masking layer comprises an organic polymer, and

wherein the first plasma comprises the source gas and a diluent gas, the source gas comprising CO and the diluent gas comprising Ar, N 2 , or He.

13 . The method of claim 10 , wherein the underlying layer comprises spin-on glass (SOG), silicon-containing antireflective coating (SiARC), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), organic BARC, or a combination thereof.

14 . A method of forming a semiconductor device, the method comprising:

forming a lithography stack on a base layer on a substrate, the lithography stack comprising a metal-based resist (MBR) layer and an underlying layer disposed below the MBR layer;

patterning the MBR layer using an extreme ultraviolet (EUV) lithography process to form a patterned MBR layer and expose a surface of a portion of the underlying layer;

depositing an overlying layer by exposing the substrate to a first plasma, the first plasma comprising a source gas that chemically and preferentially reacts with the patterned MBR layer relative to the underlying layer, the overlying layer having a first thickness over a top surface of the patterned MBR layer and a second thickness covering the exposed surface of the underlying layer, the first thickness being greater than the second thickness;

exposing the substrate to a second plasma to etch a portion of the overlying layer to expose the surface of the underlying layer covered by the overlying layer, a remaining portion of the overlying layer covering the patterned MBR layer; and

exposing the substrate to a third plasma to etch the lithography stack in a plasma chamber to form a patterned lithography stack using the remaining portion of the overlying layer and the patterned MBR layer as a first etch mask.

15 . The method of claim 14 , further comprising, using the patterned lithography stack as a second etch mask, etching a portion of the base layer.

16 . The method of claim 15 , wherein etching the portion of the base layer comprises exposing the substrate to a fourth plasma, the first plasma, the second plasma, the third plasma, and the fourth plasma being generated in the plasma chamber without removing the substrate from the plasma chamber.

17 . The method of claim 14 , wherein, after exposing the substrate to the second plasma, a thickness of the overlying layer along a sidewall of the patterned MBR layer is less than a thickness of the overlying layer over a top surface of the patterned MBR layer.

18 . The method of claim 14 ,

wherein the overlying layer comprises silicon or an organic polymer.

19 . The method of claim 14 , wherein the base layer comprises silicon dioxide, carbon doped oxide, fluorosilicate glass, porous oxide, silicon nitride, silicon oxynitride, silicon, titanium nitride, titanium, tantalum nitride, tantalum, or a combination thereof.

20 . The method of claim 14 , wherein the underlying layer comprises spin-on glass (SOG), silicon-containing antireflective coating (SiARC), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), organic BARC, or a combination thereof.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2022
From: LUTKER-LEE, KATIE; RALEY, ANGELIQUE
To: TOKYO ELECTRON LIMITED
Reel/Frame 059661/0239 →
Continuity (1)
Related Publication 20230326755A1 · Oct 12, 2023
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