IP Library Granted Patent US 11,908,699
Granted Patent B2
US 11,908,699 · App. 17/660,477 · Granted Feb 20, 2024

Semiconductor packages with die including cavities

Inventors: Michael J. Seddon (Gilbert, AZ); Francis J. Carney (Phoenix, AZ); Chee Hiong Chew (Seremban, MY); Soon Wei Wang (Seremban, MY); Eiji Kurose (Oizumi-machi, JP)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L21/302H01L21/48H01L21/561H01L21/565H01L21/78H01L23/12H01L23/3185H01L24/04H01L24/26H01L2224/94
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Quick Facts
Patent No.
US 11,908,699
App. No.
17/660,477
Granted
Feb 20, 2024
Kind
B2
Abstract

Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

Claims (24)

1. A semiconductor package comprising:

a semiconductor die comprising a first side and a second side opposite the first side;

a cavity extending into the second side of the semiconductor die and only partially through the semiconductor die;

a backmetal coupled within the cavity and directly coupled to an entirety of the second side; and

an organic material coupled over the first side of the semiconductor die and over a plurality of sidewalls of the semiconductor die;

wherein a first portion of the first side directly opposite the cavity is coplanar with a second portion of the first side at an outer edge of the first side.

2. The semiconductor package of claim 1 , wherein the organic material further comprises a die support structure.

3. The semiconductor package of claim 1 , wherein multiple surfaces of the backmetal form multiple outer surfaces of the semiconductor package.

4. The semiconductor package of claim 2 , wherein the organic material comprises a temporary die support structure.

5. The semiconductor package of claim 1 , further comprising one or more electrical contacts exposed through one or more openings in the organic material.

6. The semiconductor package of claim 1 , wherein a thinned portion of the semiconductor die is less than 5 microns thick.

7. A semiconductor package comprising:

a semiconductor die comprising a first side and a second side opposite the first side;

a cavity extending into the second side of the semiconductor die and only partially through the semiconductor die;

a backmetal coupled within the cavity; and

an organic material coupled over the first side of the semiconductor die and over an entirety of each sidewall of a plurality of sidewalls of the semiconductor die;

wherein an outer perimeter of the backmetal is a same size and shape as an outermost perimeter of the semiconductor die; and

wherein an entirety of the first side lies in a same plane and extends to the outermost perimeter of the semiconductor die.

8. The semiconductor package of claim 7 , wherein the organic material is directly coupled to the backmetal.

9. The semiconductor package of claim 7 , wherein the organic material further comprises a die support structure.

10. The semiconductor package of claim 7 , wherein a largest planar surface of the second side of the semiconductor die is within the cavity.

11. The semiconductor package of claim 7 , wherein a thinned portion of the semiconductor die is less than five microns thick.

12. The semiconductor package of claim 7 , further comprising one or more electrical contacts exposed through one or more openings in the organic material.

13. The semiconductor package of claim 7 , further comprising a conductive material coupled within the cavity.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED AT REEL 061071, FRAME 052 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, AS GRANTOR; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC., AS GRANTOR
Reel/Frame 064067/0654 →
SECURITY INTEREST Recorded Aug 4, 2022
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 061071/0525 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2022
From: SEDDON, MICHAEL J.; CARNEY, FRANCIS J.; CHEW, CHEE HIONG; WANG, SOON WEI; KUROSE, EIJI
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 059696/0880 →