Semiconductor device including multi-capping layer and method for manufacturing the same
A semiconductor device according to the disclosure includes a substrate, a transistor connected to the substrate, and a wiring structure including contact wirings electrically connected to the transistor. The wiring structure further includes a first wiring insulating layer, a first material layer contacting the first wiring insulating layer, a second material layer contacting the first material layer, and a second wiring insulating layer contacting the second material layer. The first material layer includes SiN, and the second material layer includes SiCN. A dielectric constant of the first wiring insulating layer is greater than a dielectric constant of the second wiring insulating layer.
1. A semiconductor device comprising:
a substrate;
a transistor connected to the substrate; and
a wiring structure comprising contact wirings electrically connected to the transistor,
wherein the wiring structure further comprises a first wiring insulating layer, a first material layer contacting the first wiring insulating layer, a second material layer contacting the first material layer, and a second wiring insulating layer contacting the second material layer,
wherein the first material layer comprises SiN,
wherein the second material layer comprises SiCN,
wherein a dielectric constant of the first wiring insulating layer is greater than a dielectric constant of the second wiring insulating layer, and
wherein an interfacial fracture energy between the first wiring insulating layer and the first material layer is higher than an interfacial fracture energy between the first wiring insulating layer and the second material layer.
2. The semiconductor device according to claim 1 , wherein a carbon concentration of the first wiring insulating layer is less than a carbon concentration of the second wiring insulating layer.
3. The semiconductor device according to claim 2 , wherein:
the first wiring insulating layer comprises tetraethyl orthosilicate (TEOS); and
the second wiring insulating layer comprises porous SiOCH.
4. The semiconductor device according to claim 1 , further comprising:
a penetrating via extending through the substrate,
wherein the wiring structure further comprises via wirings electrically connected to the penetrating via.
5. The semiconductor device according to claim 4 , wherein:
the via wirings comprise a first via wiring contacting the penetrating via; and
a top surface of the first via wiring contacts a bottom surface of the first material layer.
6. The semiconductor device according to claim 5 , wherein:
the contact wirings comprise a first contact wiring at a same level as the first via wiring relative to a top surface of the substrate being a base reference level; and
a top surface of the first contact wiring contacts the bottom surface of the first material layer.
7. The semiconductor device according to claim 5 , wherein:
the via wirings comprise a second via wiring contacting the first via wiring; and
the second via wiring is at least partially surrounded by the second wiring insulating layer in a plan view of the semiconductor device.
8. A semiconductor device comprising:
a substrate;
an insulating layer on the substrate;
a transistor between the substrate and the insulating layer; and
a wiring structure on the insulating layer,
wherein the wiring structure comprises a first wiring insulating layer, a first material layer contacting the first wiring insulating layer, a second material layer contacting the first material layer, and a second wiring insulating layer contacting the second material layer,
wherein the first material layer comprises SiN,
wherein the second material layer comprises SiCN,
wherein the first and second wiring insulating layers comprise an insulating material comprising carbon and oxygen,
wherein a carbon concentration of the first wiring insulating layer is less than a carbon concentration of the second wiring insulating layer, and
wherein an interfacial fracture energy between the second wiring insulating layer and the second material layer is higher than an interfacial fracture energy between the second wiring insulating layer and the first material layer.
9. The semiconductor device according to claim 8 , wherein:
the first wiring insulating layer comprises tetraethyl orthosilicate (TEOS); and
the second wiring insulating layer comprises porous SiOCH.
10. The semiconductor device according to claim 8 , wherein:
the wiring structure further comprises a third material layer contacting the second wiring insulating layer; and
the third material layer comprises SiCN.
11. The semiconductor device according to claim 10 , wherein:
the wiring structure further comprises a fourth material layer contacting the third material layer; and
the fourth material layer comprises SiN.
12. The semiconductor device according to claim 11 , wherein:
the wiring structure further comprises a third wiring insulating layer contacting the fourth material layer; and
the third wiring insulating layer comprises a same material as the first wiring insulating layer.
13. The semiconductor device according to claim 8 , wherein:
the wiring structure further comprises a single capping layer contacting the second wiring insulating layer, and a third wiring insulating layer contacting the single capping layer; and
the third wiring insulating layer comprises a same material as the second wiring insulating layer.
14. The semiconductor device according to claim 8 , wherein:
the wiring structure further comprises a third material layer contacting the first wiring insulating layer; and
the third material layer comprises SiN.
15. The semiconductor device according to claim 14 , wherein:
the wiring structure further comprises a fourth material layer contacting the third material layer; and
the fourth material layer comprises SiCN.
16. A semiconductor device comprising:
a substrate;
an insulating layer on the substrate;
a transistor between the substrate and the insulating layer; and
a wiring structure on the insulating layer,
wherein the wiring structure comprises a first wiring and a second wiring contacting each other, a first wiring insulating layer at least partially surrounding the first wiring in a plan view of the semiconductor device, a second wiring insulating layer at least partially surrounding the second wiring in the plan view of the semiconductor device, and a multi-capping layer interposed between the first and second wiring insulating layers,
wherein a dielectric constant of the first wiring insulating layer is greater than a dielectric constant of the second wiring insulating layer,
wherein the multi-capping layer comprises a first material layer and a second material layer respectively having different carbon concentrations,
wherein an average of interfacial fracture energies at a plurality of positions between the first wiring insulating layer and the first material layer is higher than an average of interfacial fracture energies at a plurality of positions between the first wiring insulating layer and the second material layer, and
wherein an average of interfacial fracture energies at a plurality of positions between the second wiring insulating layer and the second material layer is higher than an average of interfacial fracture energies at a plurality of positions between the second wiring insulating layer and the first material layer.
17. The semiconductor device according to claim 16 , wherein:
the first wiring insulating layer contacts the first material layer;
the second wiring insulating layer contacts the second material layer; and
a carbon concentration of the second material layer is greater than a carbon concentration of the first material layer.
18. The semiconductor device according to claim 17 , wherein:
the first material layer comprises SiN; and
the second material layer comprises SiCN.
19. The semiconductor device according to claim 16 , wherein:
the first and second wiring insulating layers comprise an insulating material comprising carbon and oxygen; and
a carbon concentration of the first wiring insulating layer is less than a carbon concentration of the second wiring insulating layer.
20. The semiconductor device according to claim 16 , wherein the second wiring extends through the multi-capping layer.