Semiconductor structure and manufacturing method thereof
Embodiments of the present disclosure belong to the technical field of semiconductor structure manufacturing, and specifically provide a semiconductor structure and a manufacturing method thereof. The manufacturing method specifically includes: a first gate structure on a substrate, a first conductive region and a second conductive region, wherein the first conductive region and the second conductive region are located at two sides of the first gate structure, and in a direction perpendicular to the substrate, the first conductive region and the second conductive region are located at different height positions.
1. A semiconductor structure, comprising:
a first gate structure on a substrate, a first conductive region and a second conductive region, wherein the first conductive region and the second conductive region are located at two sides of the first gate structure, and in a direction perpendicular to the substrate, the first conductive region and the second conductive region are located at different height positions; and
a second gate structure on the substrate and a third conductive region, wherein the first conductive region and the third conductive region are located at two sides of the second gate structure, and in the direction perpendicular to the substrate, the third conductive region and the first conductive region are located at different height positions; and
wherein the substrate is of a U-shaped structure, a position of the first conductive region on a surface of the substrate is lower than a position of the second conductive region on a surface of the substrate, and the position of the first conductive region on the surface of the substrate is lower than a position of the third conductive region on a surface of the substrate.
2. The semiconductor structure according to claim 1 , wherein a first channel region is formed between the first conductive region and the second conductive region and at a side close to the first gate structure, and the first channel region is provided with a bending structure.
3. The semiconductor structure according to claim 2 , wherein there is a height difference between the first conductive region and the second conductive region, and an absolute value of the height difference between the first conductive region and the second conductive region is greater than zero and less than a length of the first channel region.
4. The semiconductor structure according to claim 1 , wherein the first gate structure comprises a first gate conductor block and a first gate dielectric layer, the first gate dielectric layer is located between the first gate structure and the substrate, and the first gate dielectric layer is provided with a bending structure.
5. The semiconductor structure according to claim 4 , wherein the first gate dielectric layer is distributed along a horizontal direction of the substrate and a vertical direction of the substrate, and the first gate dielectric layer is distributed continuously.
6. The semiconductor structure according to claim 1 , wherein a second channel region is formed between the third conductive region and the first conductive region and at a side close to the second gate structure, and the second channel region is provided with a bending structure.
7. The semiconductor structure according to claim 6 , wherein there is a height difference between the third conductive region and the first conductive region, and an absolute value of the height difference between the third conductive region and the first conductive region is greater than zero and less than a length of the second channel region.
8. The semiconductor structure according to claim 1 , wherein the second gate structure comprises a second gate conductor block and a second gate dielectric layer, the second gate dielectric layer is located between the second gate structure and the substrate, and the second gate dielectric layer is provided with a bending structure.
9. The semiconductor structure according to claim 8 , wherein the second gate dielectric layer is distributed along a horizontal direction of the substrate and a vertical direction of the substrate, and the second gate dielectric layer is distributed continuously.
10. The semiconductor structure according to claim 1 , wherein in the direction perpendicular to the substrate, the first gate structure, the first conductive region, the second conductive region, the second gate, and the third conductive region are electrically connected through a first plug, a second plug, a third plug, a fourth plug, and a fifth plug, respectively; wherein the third plug penetrates into the second conductive region, and the fifth plug penetrates into the third conductive region.