Approach to bottom dielectric isolation for vertical transport fin field effect transistors
A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.
1. A method of forming a vertical transport fin field effect transistor, comprising:
forming one or more vertical fins on a substrate;
forming an extension region at the base of at least one of the one or more vertical fins;
forming a spacer layer on the substrate and exposed surfaces of the one or more vertical fins;
forming a gauge layer on the spacer layer;
removing a portion of the gauge layer to form one or more gauge sections on the spacer layer, wherein a portion of the spacer layer on the one or more vertical fins is exposed by removing the portion of the gauge layer; and
removing the exposed portion of the spacer layer to form an L-shaped or U-shaped spacer trough.
2. The method of forming a vertical transport fin field effect transistor of claim 1 , further comprising, forming a liner layer between the substrate and the spacer layer and between the one or more vertical fins and the spacer layer, and removing a portion of the liner layer on the one or more vertical fins exposed by removing the exposed portion of the spacer layer.
3. The method of forming a vertical transport fin field effect transistor of claim 1 , further comprising, removing the one or more gauge sections to expose an inside sidewall of the L-shaped or U-shaped spacer trough.
4. The method of forming a vertical transport fin field effect transistor of claim 3 , further comprising, forming a gate dielectric layer on the exposed portion of the one or more vertical fins and inside sidewall of the L-shaped or U-shaped spacer trough.
5. The method of forming a vertical transport fin field effect transistor of claim 4 , wherein the material of the L-shaped or U-shaped spacer trough is silicon nitride (SiN), and wherein the inside sidewall has a height above the trough surface in the range of about 1 nm to about 5 nm.
6. The method of forming a vertical transport fin field effect transistor of claim 4 , further comprising, forming a top source/drain on the top surface of the at least one of the one or more vertical fins, and a bottom source/drain below the at least one of the one or more vertical fins.
7. The method of forming a vertical transport fin field effect transistor of claim 6 , further comprising, forming a work function layer on the exposed surfaces of the gate dielectric layer, and forming a gate fill layer on the work function layer.
8. The method of forming a vertical transport fin field effect transistor of claim 7 , wherein the gate fill layer is above the L-shaped or U-shaped spacer trough.
9. The method of forming a vertical transport fin field effect transistor of claim 8 , further comprising forming a contact region liner on a portion of the gate fill layer.