Template for nanosheet source drain formation with bottom dielectric
Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is crystallized. Epitaxially growth of the source and drain regions then proceeds, which growth advantageously occurring on the bottom and sidewalls of the source and drain regions.
1 . A method of forming a semiconductor device, the method comprising:
forming a superlattice structure on a top surface of a bottom dielectric isolation layer on a substrate, the superlattice structure comprising a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs and the bottom dielectric isolation layer selected from the group consisting of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-K material;
forming a source trench and a drain trench adjacent to the superlattice structure on the bottom dielectric isolation layer on the substrate;
depositing a template material in the source trench and in the drain trench directly on the bottom dielectric isolation layer;
crystallizing the template material by one or more of rapid thermal processing (RTP) anneal or laser anneal at a temperature in a range of from 600° C. to 900° C. in an atmosphere of hydrogen (H 2 ) gas and oxygen (O 2 ) to form a crystallized template material directly on the bottom dielectric isolation layer; and
forming a source region and a drain region on the crystallized template material.
2 . The method of claim 1 , wherein the template material is amorphous.
3 . The method of claim 2 , wherein the template material comprises silicon (Si), silicon germanium (SiGe), titanium (Ti), zirconium (Zr), and hafnium (Hf).
4 . The method of claim 2 , wherein the template material has a thickness in a range of from 2 nm to 50 nm.
5 . The method of claim 1 , wherein the plurality of semiconductor material layers and the plurality of horizontal channel layers independently comprise one or more of silicon germanium (SiGe) and silicon (Si).
6 . The method of claim 1 , wherein forming the source region and the drain region comprises growing an epitaxial layer on the crystallized template material.
7 . The method of claim 1 , wherein the source region and the drain region are independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).
8 . The method of claim 1 , further comprising forming a gate structure on a top surface of the superlattice structure.
9 . The method of claim 8 , further comprising forming a dielectric layer on the gate structure and on the superlattice structure.
10 . The method of claim 9 , wherein the gate structure comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and titanium aluminum (TiAl).
11 . A method of forming a semiconductor device, the method comprising:
forming a superlattice structure on a top surface of a bottom dielectric isolation layer on a substrate, the superlattice structure comprising a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs and the bottom dielectric isolation layer selected from the group consisting of silicon oxide (SiO x ), silicon nitride (SiN), silicon carbide (SiC), and a high-κ material;
forming a gate structure on a top surface of the superlattice structure;
forming a dielectric layer on the gate structure and on the superlattice structure;
forming a source trench and a drain trench adjacent to the superlattice structure on the bottom dielectric isolation layer on the substrate;
depositing a template material in the source trench and in the drain trench directly on the bottom dielectric isolation layer;
annealing the substrate by one or more of rapid thermal processing (RTP) anneal or laser anneal at a temperature in a range of from 600° C. to 900° C. in an atmosphere of hydrogen (H 2 ) gas and oxygen (O 2 ) to crystallize the template material to form a crystallized template material directly on the bottom dielectric isolation layer; and
forming a source region and a drain region on the crystallized template material.
12 . The method of claim 11 , wherein the template material is amorphous and has a thickness in a range of from 2 nm to 50 nm.
13 . The method of claim 12 , wherein the template material comprises silicon (Si), silicon germanium (SiGe), titanium (Ti), zirconium (Zr), and hafnium (Hf).
14 . The method of claim 11 , wherein the plurality of semiconductor material layers and the plurality of horizontal channel layers independently comprise one or more of silicon germanium (SiGe) and silicon (Si).
15 . The method of claim 11 , wherein forming the source region and the drain region comprises growing an epitaxial layer on the crystallized template material.
16 . The method of claim 11 , wherein the source region and the drain region are independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).