IP Library Granted Patent US 11,557,652
Granted Patent B2
US 11,557,652 · App. 16/562,693 · Granted Jan 17, 2023

Metal source/drain-based MOSFET and method for fabricating the same

Inventors: Rock Hyun Baek (Pohang-si, KR); Jun Sik Yoon (Pohang-si, KR); Jin Su Jeong (Daegu, KR); Seung Hwan Lee (Busan, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L29/0847H01L29/66522
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Quick Facts
Patent No.
US 11,557,652
App. No.
16/562,693
Granted
Jan 17, 2023
Kind
B2
Abstract

Disclosed is a metal source/drain-based field effect transistor having a structure that replaces a portion of a semiconductor of a source/drain with a metal and a method of manufacturing the same. By replacing the source/drain region with the source/drain metal region, increase of the parasitic resistance of a conventional three-dimensional MOSFET of several tens of nanometers, lattice mismatch of the source/drain during selective epitaxial growth, and self-heating effect can be fundamentally solved. Further, since the metal is deposited after the partial etching of the source/drain region or the selective epitaxial growth is partially performed under the conventional CMOS process, the process can be performed without using any additional mask.

Claims (55)

1. A metal source/drain-based MOSFET comprising:

a stopper; a channel layer on the stopper;

a first insulating layer on the channel layer;

a second insulating layer between the stopper and the first insulating layer, and alternatively with the channel layer;

a gate on the channel layer and in the first insulating layer, wherein the gate comprises a gate oxide contacting the channel layer and the first insulating layer;

a source/drain region on the stopper and having a first side surface and a second side surface opposite the first side surface, the first side surface contacting the channel layer; and

a source/drain metal region directly contacting the second side surface of the source/drain region, wherein

a topmost surface of the source/drain region is parallel to a surface of the stopper, at a level above a bottom level of a topmost gate, and directly contacts an overhanging outer portion of the first insulating layer at the level above the bottom level of the topmost gate,

a lowermost surface of the source/drain metal region is located at a level below a top level of a lowermost channel layer, and the first insulating layer further includes an overhanging inner portion that directly contacts a top level of the topmost gate, wherein a top surface of the gate oxide directly contacts a bottom surface of the overhanging inner portion, and

the bottom of the overhanging portion is in direct contact with all of the top surface of the gate oxide.

2. The metal source/drain-based MOSFET of claim 1 , wherein the first side surface of the source/drain region is flush with a side surface the first insulating layer.

3. The metal source/drain-based MOSFET of claim 1 , wherein the first side surface of the source/drain region has a protruding shape with respect to the channel.

4. The metal source/drain-based MOSFET of claim 1 , wherein the gate comprises:

a metal barrier on the gate oxide; and

a work function control metal filling an interior of the metal barrier.

5. The metal source/drain-based MOSFET of claim 4 , further comprising:

a gate metal region on the metal barrier and on the work function control metal.

6. The metal source/drain-based MOSFET of claim 4 , further comprising:

a gate metal region on the gate oxide, the metal barrier and the work function control metal.

7. The metal source/drain-based MOSFET of claim 1 , wherein the source/drain region has an etching portion.

8. The metal source/drain-based MOSFET of claim 1 , wherein the source/drain region includes any one of silicon, germanium, tin, and group 3-5 compounds, and is of at least one of a crystalline phase, a poly-crystalline phase, or an amorphous phase.

9. The metal source/drain-based MOSFET of claim 1 , wherein the source/drain metal region includes at least one of aluminum, titanium, copper, nickel, and tungsten.

10. The metal source/drain-based MOSFET of claim 1 , wherein the stopper includes at least one of a p-type or n-type dopant,

wherein at least one of B, BF2, Al or Ga is included in the stopper in response to the stopper being p-type, and

wherein at least one of P, As or Sb is included in the stopper in response to the stopper being n-type.

11. The metal source/drain-based MOSFET of claim 2 , wherein the gate is at a spaced space between the channel layers.

12. The metal source/drain-based MOSFET of claim 1 , wherein the second insulating layer is in a spaced space between the channel layers, and on both sides of the gate.

13. The metal source/drain-based MOSFET of claim 1 , wherein the source/drain region has an “L”-shaped cross-sectional profile, with a bottom of the “L” directly contacting the stopper and a side of the “L” directly contacting the second insulating layer.

14. The metal source/drain-based MOSFET of claim 1 , wherein the source/drain region directly contacts the stopper.

15. The metal source/drain-based MOSFET of claim 1 , wherein the channel layer is provided in plurality, each of the plurality of channel layers stacked in a vertical direction perpendicular to an upper surface of the stopper, and

a bottom surface of the source/drain metal region directly contacts the source/drain region at a lower level than a topmost one of the plurality of channel layers.

16. The metal source/drain-based MOSFET of claim 1 , wherein the source/drain metal region directly contacts the stopper.

17. The metal source/drain-based MOSFET of claim 1 , wherein the source/drain region has a bottom surface directly contacting the stopper.

18. The metal source/drain-based MOSFET of claim 1 , wherein a concentration of impurities included in the source/drain region has a range of between 10{circumflex over ( )}19 cm−3 to 10{circumflex over ( )}21 cm−3.

19. The metal source/drain-based MOSFET of claim 1 , wherein the source/drain region defines an etching portion, the etching portion having a recessed profile, and

the source/drain metal region fills the etching portion.

20. The metal source/drain-based MOSFET of claim 1 , wherein the source/drain metal region includes at least one of aluminum, titanium, copper, or nickel.

21. The metal source/drain-based MOSFET of claim 1 , wherein the source/drain metal region has a bottom surface that directly contacts the stopper.

22. A metal source/drain-based MOSFET comprising:

a stopper;

a plurality of channel layers on the stopper;

a first insulating layer directly on a topmost one of the plurality of channel layers;

a plurality of second insulating layers between the stopper and the first insulating layer, and alternatively with the channel layer;

a plurality of gates on the plurality of channel layers and in the first insulating layer, wherein each of the plurality of gates comprise a gate oxide contacting a respective one of the channel layer and the first insulating layer;

a source/drain region directly on the stopper and having a first side surface and a second side surface opposite the first side surface, the first side surface directly contacting each of the plurality of channel layers; and

a source/drain metal region directly contacting the second side surface of the source/drain region, wherein

a top of an uppermost surface of the source/drain region contacts the source/drain metal region at a level above a bottom surface of a topmost one of the plurality of gates and is above the bottom surface of the topmost one of the plurality of gates,

a top of a lowermost surface of the source/drain region, different from the uppermost surface of the source/drain region, contacts the source/drain metal region,

the top of the uppermost surface the source/drain region contacts an overhanging outer portion of the first insulating layer at a level above a bottom level of the topmost one of the plurality of gates,

a lowermost surface of the source/drain metal region is at a level below a top level of a lowermost one of the plurality of channel layers,

the first insulating layer further includes an overhanging inner portion that directly contacts a top level of the topmost one of the plurality of gates, and

all top surfaces of the gate oxide of the topmost one directly contacts a bottom surface of the overhanging inner portion, and the top surfaces are planar with a top surface of a gate conductor included in the topmost one of the plurality of gates.

23. The metal source/drain based MOSFET of claim 22 , wherein the source/drain region includes a bottom portion directly contacting the stopper.

24. The metal source/drain based MOSFET of claim 1 , wherein bottom of the overhanging inner portion is at least partially in direct contact with a metal barrier included in the gate.

25. The metal source/drain based MOSFET of claim 24 , wherein the bottom surface of the overhanging inner portion is planar with a bottom surface of a gate metal region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2020
From: POSTECH ACADEMY - INDUSTRY FOUNDATION
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 054857/0570 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2019
From: BAEK, ROCK HYUN; YOON, JUN SIK; JEONG, JIN SU; LEE, SEUNG HWAN
To: POSTECH ACADEMY - INDUSTRY FOUNDATION
Reel/Frame 050290/0875 →
Priority Claims (1)
KR 10-2018-0114050 · Sep 21, 2018 · national
Continuity (1)
Related Publication 20200098862A1 · Mar 26, 2020