Gate-all-around integrated circuit structures having insulator substrate
Gate-all-around integrated circuit structures having an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator substrate, are described. For example, an integrated circuit structure includes a semiconductor fin on an insulator substrate. A vertical arrangement of horizontal nanowires is over the semiconductor fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires, and the gate stack is overlying a channel region of the semiconductor fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires and the semiconductor fin.
1. An integrated circuit structure, comprising:
a semiconductor fin on and in direct physical contact with an insulator substrate;
a vertical arrangement of horizontal nanowires over the semiconductor fin;
a gate stack surrounding a channel region of the vertical arrangement of horizontal nanowires, the gate stack overlying a channel region of the semiconductor fin, and the gate stack comprising a gate electrode vertically between a bottommost one of the vertical arrangement of horizontal nanowires and a top of the semiconductor fin; and
a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal nanowires and the semiconductor fin, wherein one or both of the pair of epitaxial source or drain structures is vertically overlapping with a top surface of an uppermost one of the vertical arrangement of horizontal nanowires and is in direct physical contact with the top surface of the uppermost one of the vertical arrangement of horizontal nanowires.
2. The integrated circuit structure of claim 1 , wherein the semiconductor fin has a vertical thickness approximately the same as a vertical thickness of each of the nanowires of the vertical arrangement of horizontal nanowires.
3. The integrated circuit structure of claim 1 , wherein the semiconductor fin has a vertical thickness greater than a vertical thickness of each of the nanowires of the vertical arrangement of horizontal nanowires.
4. The integrated circuit structure of claim 1 , wherein the semiconductor fin has a vertical thickness less than a vertical thickness of each of the nanowires of the vertical arrangement of horizontal nanowires.
5. The integrated circuit structure of claim 1 , wherein the semiconductor fin and the vertical arrangement of horizontal nanowires comprise silicon.
6. The integrated circuit structure of claim 1 , wherein the semiconductor fin and the vertical arrangement of horizontal nanowires comprise silicon germanium or a group III-V material.
7. The integrated circuit structure of claim 1 , wherein the insulator substrate comprises a layer of silicon oxide, and the semiconductor fin is on the layer of silicon oxide.
8. The integrated circuit structure of claim 1 , wherein the insulator substrate comprises a layer of silicon nitride, and the semiconductor fin is on the layer of silicon nitride.
9. The integrated circuit structure of claim 1 , wherein a bottom of the pair of epitaxial source or drain structures is on the insulator substrate.
10. The integrated circuit structure of claim 9 , wherein the bottom of the pair of epitaxial source or drain structures is co-planar with a bottom of the semiconductor fin.
11. The integrated circuit structure of claim 9 , wherein the bottom of the pair of epitaxial source or drain structures is on a surface of a recess in the insulator substrate, and the bottom of the pair of epitaxial source or drain structures is below a bottom of the semiconductor fin.
12. The integrated circuit structure of claim 1 , wherein the pair of epitaxial source or drain structures is a pair of non-discrete epitaxial source or drain structures.
13. The integrated circuit structure of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.
14. A method of fabricating an integrated circuit structure, the method comprising:
forming a vertical arrangement of horizontal nanowires above a semiconductor fin above a semiconductor substrate;
forming a gate stack surrounding a channel region of the vertical arrangement of horizontal nanowires, the gate stack overlying a channel region of the semiconductor fin;
forming a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal nanowires and the semiconductor fin, wherein one or both of the pair of epitaxial source or drain structures is vertically overlapping with a top surface of an uppermost one of the vertical arrangement of horizontal nanowires and is in direct physical contact with the top surface of the uppermost one of the vertical arrangement of horizontal nanowires;
removing the semiconductor substrate to expose a bottom of the semiconductor fin and a bottom of the epitaxial source or drain structures; and
bonding an insulator substrate to the bottom of the semiconductor fin and to the bottom of the epitaxial source or drain structures.
15. The method of claim 14 , wherein forming the pair of epitaxial source or drain structures comprises forming a non-discrete pair of epitaxial source or drain structures.
16. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a semiconductor fin on and in direct physical contact with an insulator substrate;
a vertical arrangement of horizontal nanowires over the semiconductor fin;
a gate stack surrounding a channel region of the vertical arrangement of horizontal nanowires, the gate stack overlying a channel region of the semiconductor fin, and the gate stack comprising a gate electrode vertically between a bottommost one of the vertical arrangement of horizontal nanowires and a top of the semiconductor fin; and
a pair of epitaxial source or drain structures at first and second ends of the vertical
arrangement of horizontal nanowires and the semiconductor fin, wherein one or both of the pair of epitaxial source or drain structures is vertically overlapping with a top surface of an uppermost one of the vertical arrangement of horizontal nanowires and is in direct physical contact with the top surface of the uppermost one of the vertical arrangement of horizontal nanowires.
17. The computing device of claim 16 , further comprising:
a memory coupled to the board.
18. The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19. The computing device of claim 16 , wherein the component is a packaged integrated circuit die.
20. The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.