Semiconductor device and method
View Patent ↗A device includes a first source/drain region including: a first metal layer including a first metal; and a conductive two-dimensional material on the first metal layer; an isolation layer physically contacting a sidewall of the first metal layer, wherein the conductive two-dimensional material protrudes above the isolation layer; a two-dimensional semiconductor material on the isolation layer, wherein a sidewall of the two-dimensional semiconductor material physically contacts a sidewall of the conductive two-dimensional material; and a gate stack on the two-dimensional semiconductor material.
1. A device comprising:
a first source/drain region comprising:
a first metal layer comprising a first metal; and
a conductive two-dimensional material on the first metal layer;
an isolation layer physically contacting a sidewall of the first metal layer, wherein the conductive two-dimensional material protrudes above the isolation layer;
a two-dimensional semiconductor material on the isolation layer, wherein a sidewall of the two-dimensional semiconductor material physically contacts a sidewall of the conductive two-dimensional material; and
a gate stack on the two-dimensional semiconductor material.
2. The device of claim 1 further comprising a doping layer extending on the conductive two-dimensional material and on the gate stack, wherein the doping layer provides a doping effect to the conductive two-dimensional material.
3. The device of claim 2 , wherein the doping layer comprises an oxide.
4. The device of claim 1 , wherein top surfaces of the two-dimensional semiconductor material are free of the conductive two-dimensional material.
5. The device of claim 1 , wherein the conductive two-dimensional material comprises the first metal.
6. The device of claim 5 , wherein the first metal is a transition metal.
7. The device of claim 1 , wherein the two-dimensional semiconductor material comprises a transition metal dichalcogenide.
8. The device of claim 1 , wherein the conductive two-dimensional material protrudes above the two-dimensional semiconductor material.
9. A device comprising:
a first transistor comprising:
a first drain region comprising a first two-dimensional (2D) contact material over a first metal material;
a first source region comprising the first 2D contact material over the first metal material;
a first 2D channel material extending from the first drain region to the first source region, wherein the first 2D channel material physically contacts a sidewall of the first 2D contact material of the first drain region and a sidewall of the first 2D contact material of the first source region;
a first gate dielectric material on the first 2D channel material;
a first gate electrode material on the first gate dielectric material; and
a first doping layer extending on the first drain region, the first source region, the first gate dielectric material, and the first gate electrode material.
10. The device of claim 9 further comprising a second transistor adjacent the first transistor, wherein the second transistor comprises:
a second drain region comprising a second 2D contact material over a second metal material;
a second source region comprising the second 2D contact material over the second metal material;
a second 2D channel material extending from the second drain region to the second source region, wherein the second 2D channel material physically contacts a sidewall of the second 2D contact material of the second drain region and a sidewall of the second 2D contact material of the second source region;
a second gate dielectric material on the second 2D channel material;
a second gate electrode material on the second gate dielectric material; and
a second doping layer extending on the second drain region, the second source region, the second gate dielectric material, and the second gate electrode material.
11. The device of claim 10 , wherein the first transistor is p-type and the second transistor is n-type.
12. The device of claim 10 , wherein the first drain region physically and electrically contacts the second drain region.
13. The device of claim 10 , wherein the first 2D channel material and the second 2D channel material comprise the same material.
14. The device of claim 10 , wherein the first drain region is adjacent the second drain region, wherein the first source region is adjacent the second source region, and further comprising a gate contact that physically and electrically contacts the first gate electrode material and the second gate electrode material.
15. The device of claim 9 , wherein the first 2D contact material physically contacts a top surface of the first 2D channel material.
16. The device of claim 9 further comprising a source/drain contact extending through the first 2D contact material to physically contact the first metal material.
17. A device comprising:
a low-dimensional semiconductor layer on an isolation layer;
a gate structure on the low-dimensional semiconductor layer;
a metal material in the isolation layer adjacent the low-dimensional semiconductor layer;
a low-dimensional contact layer on the metal material, wherein a sidewall of the low-dimensional contact layer physically and electrically contacts a sidewall of the low-dimensional semiconductor layer; and
a doping layer over the low-dimensional contact layer and the gate structure.
18. The device of claim 17 , wherein an upper portion of the metal material comprises sulfur or selenium.
19. The device of claim 17 further comprising a source/drain contact extending through the doping layer and the low-dimensional contact layer to the metal material.
20. The device of claim 17 further comprising a gate contact extending through the doping layer that physically and electrically contacts the gate structure.