IP Library Granted Patent US 10,872,973
Granted Patent B2
US 10,872,973 · App. 16/236,004 · Granted Dec 22, 2020

Semiconductor structures with two-dimensional materials

Inventors: Shih-Yen Lin (Tainan, TW); Hsuan-An Chen (Chiayi, TW)
Assignees: Taiwan Semiconductor Manufacturing Co., Ltd.; National Taiwan University
H01L29/7606H01L21/02568H01L29/24H01L29/66969
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Quick Facts
Patent No.
US 10,872,973
App. No.
16/236,004
Granted
Dec 22, 2020
Kind
B2
Abstract

The current disclosure describes semiconductor devices, e.g., transistors, including a substrate, a semiconductor region including, at the surface, monolayer MoS 2 and/or other monolayer material over the substrate, and a terminal structure over the semiconductor region, which includes a different monolayer material grown directly over the semiconductor region.

Claims (29)

1. A method, comprising:

receiving a wafer including a substrate and a first layer of a first two-dimensional material over the substrate;

forming a first pattern of the first two-dimensional material by patterning the first layer; and

selectively forming a second layer of a second two-dimensional material over the first pattern, the second layer of the second two-dimensional material overlapping only the first pattern.

2. The method of claim 1 , further comprising thinning the first layer of the first two-dimensional material such that the first layer of the first two-dimensional material exhibits a semiconductor property.

3. The method of claim 2 , further comprising heating the substrate and the first pattern of the first two dimensional material before forming the second layer of the second two-dimensional material.

4. The method of claim 1 , wherein the first two-dimensional material is a transition metal dichalcogenide (TMD) material.

5. The method of claim 1 , wherein the first two-dimensional material exhibits a semiconductor property.

6. The method of claim 1 , wherein the first two-dimensional material is molybdenum disulfide with a thickness ranging from about two monolayers of two-dimensional molybdenum disulfide to about six monolayers of two-dimensional molybdenum disulfide.

7. The method of claim 1 , wherein the selectively forming the second layer of the second two-dimensional material over the first pattern includes growing the second two-dimensional material globally over the wafer with a growth condition that prevents the second two-dimensional material from bonding to a surface of the wafer outside the first pattern.

8. The method of claim 7 , wherein the second two-dimensional material is antimonene and the growth condition includes a growth temperature higher than 150° C.

9. A method, comprising:

receiving a wafer including a substrate and a first layer of a first two-dimensional material over the substrate;

forming a first pattern of the first two-dimensional material by patterning the first layer of the first two-dimensional material, the first pattern of the first two-dimensional material exhibiting a semiconductor property;

forming a second layer of a second two-dimensional material over the first pattern of the first two-dimensional material, the second layer of the second two-dimensional material having sidewalls that are coterminous with sidewalls of the first pattern;

forming a conductive layer over the second layer of the second two-dimensional material;

patterning the conductive layer and the second layer of the second two-dimensional material to form a source structure and a drain structure and an exposed portion of the first pattern between the source structure and the drain structure; and

forming a gate structure over the exposed portion of the first pattern.

10. The method of claim 9 , further comprising treating the second layer of the second two-dimensional material such that the second layer exhibits a semimetal property.

11. The method of claim 9 , wherein the first two-dimensional material is molybdenum disulfide.

12. The method of claim 9 , wherein the second two-dimensional material is antimonene.

13. The method of claim 9 , further comprising annealing the second layer of the second two-dimensional material.

14. The method of claim 13 , wherein the annealing is conducted after the conductive layer is formed.

15. The method of claim 9 , further comprising reducing a thickness of the first layer of the first two-dimensional material.

16. The method of claim 1 , wherein the second-two dimensional material exhibits a semimetal property.

17. The method of claim 8 , wherein the second two-dimensional material is a β allotrope of antimonene.

18. The method of claim 1 , further comprising forming a conductive layer over the second two-dimensional material.

19. The method of claim 18 , further comprising patterning the conductive layer and the second two-dimensional material together to form a source/drain structure.

20. The method of claim 12 , wherein the second two-dimensional material is a β allotrope of antimonene.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2019
From: LIN, SHIH-YEN; CHEN, HSUAN-AN
To: NATIONAL TAIWAN UNIVERSITY; TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 047902/0387 →
Continuity (2)
Provisional Application 62691540 · Jun 28, 2018
Related Publication 20200006541A1 · Jan 2, 2020
Cited By (4)
US 12,249,643 US 12,324,197 US 12,713,661 US 12,720,800