Architectural support for persistent applications
Illustrative embodiments are directed to methods, apparatus and computer program products for caching at least a fraction of data stored in a non-volatile memory in a mirror region of a dynamic random access memory. A memory controller hub of a processor chip coupled to both the non-volatile memory and the dynamic random access memory is configured to, when an update to the dynamic random access memory is cached in the mirror region of the dynamic random access memory, use the memory controller hub to write the update directly to the mirror region of the dynamic random access memory and concurrently mirror the update to the non-volatile memory to provide coherent persistent durability of the update. When a read from the dynamic random access memory is cached in the mirror region of the dynamic random access memory, embodiments can use the memory controller hub to serve the read directly from the mirror region of the dynamic random access memory to optimize read operations of persistent objects.
1. A method of architectural support of hybrid memory system persistent applications, the method comprising:
caching at least a fraction of data stored in a non-volatile memory in a mirror region of a dynamic random access memory, the dynamic random access memory comprising a mirror mapping table comprising a hardware managed table,
wherein a memory controller hub of a processor chip coupled to both the non-volatile memory and the dynamic random access memory is configured to, when a first update to the dynamic random access memory is cached in the mirror region of the dynamic random access memory, using the memory controller hub to both write the update directly to the mirror region of the dynamic random access memory and concurrently mirror the update to the non-volatile memory providing coherent persistent durability of the update,
wherein the hardware managed table includes for each mirrored page a group ID, a TAG (non-volatile memory page address) and a dynamic random access memory address.
2. The method of claim 1 , when a read from the dynamic random access memory is cached in the mirror region of the dynamic random access memory, using the memory controller hub to serve the read directly from the mirror region of the dynamic random access memory.
3. The method of claim 1 , when a second update to the dynamic random access memory is not cached in the mirror region of the dynamic random access memory, not concurrently mirroring the update to the non-volatile memory.
4. The method of claim 1 , wherein the memory controller hub supports both memory mode and application direct mode.
5. The method of claim 1 , wherein the memory controller hub transparently ensures durability of updates to persistent pages that are also cached in DRAM.
6. The method of claim 1 , wherein the memory controller hub is configured to, when a read from a memory block is cached in the mirror region of the dynamic random access memory and pressure at the dynamic random access memory is above a threshold, bypassing the mirror region of the dynamic random access memory and accessing the read in the non-volatile memory.
7. The method of claim 1 , wherein the memory controller hub is configured to, when a plurality of pages is cached in the mirror region of the dynamic random access memory, access the plurality of pages in the dynamic random access memory using bank level parallelism, instead of accesses to the non-volatile memory.
8. The method of claim 1 , wherein the memory controller hub is configured to implement multi-queue page eviction based on a least recently used algorithm wherein, when a threshold to be mirrored is reached, M least recently used queues of block descriptors are defined wherein each descriptor comprises a block number, a reference counter and a logical expiration time, wherein a page is cached in the mirror region of the dynamic random access memory using the memory controller hub to both write the page directly to the mirror region of the dynamic random access memory and concurrently mirror the page to the non-volatile memory, to keep hot pages in the mirror region of the dynamic random access memory.
9. A method of architectural support of hybrid memory system persistent applications, the method comprising:
caching at least a fraction of data stored in a non-volatile memory in a mirror region of a dynamic random access memory,
wherein a memory controller hub of a processor chip coupled to both the non-volatile memory and the dynamic random access memory is configured to, when an update to the dynamic random access memory is cached in the mirror region of the dynamic random access memory, using the memory controller hub to both write the update directly to the mirror region of the dynamic random access memory and concurrently mirror the update to the non-volatile memory to provide coherent persistent durability of the update,
wherein a mirror mapping table of the dynamic random access memory comprises a hardware managed table including for each mirrored page a group ID, a TAG (non-volatile memory page address) and a dynamic random access memory address.
10. An apparatus for architectural support of hybrid memory system persistent applications, the apparatus comprising:
a processor chip comprising a core, a cache, and a memory controller hub;
a non-volatile memory coupled to the processor chip; and
a dynamic random access memory coupled to the processor chip, the dynamic random access memory comprising a mirror mapping table comprising a hardware managed table, and a mirror region,
wherein the dynamic random access memory caches at least fraction of data stored in the non-volatile memory in the mirror region of the dynamic random access memory,
wherein the memory controller hub is configured to, when a first update to the dynamic random access memory is cached in the mirror region of the dynamic random access memory, using the memory controller hub to both write the update directly to the mirror region of the dynamic random access memory and concurrently mirror the update to the non-volatile memory providing coherent persistent durability of the update,
wherein the hardware managed table includes for each mirrored page a group ID, a TAG (non-volatile memory page address) and a dynamic random access memory address.
11. The apparatus of claim 10 , when a read from the dynamic random access memory is cached in the mirror region of the dynamic random access memory, using the memory controller hub to serve the read directly from the mirror region of the dynamic random access memory.
12. The apparatus of claim 10 , when a second update to the dynamic random access memory is not cached in the mirror region of the dynamic random access memory, not concurrently mirroring the update to the non-volatile memory.
13. The apparatus of claim 10 , wherein the memory controller hub supports both memory mode and application direct mode.
14. The apparatus of claim 10 , wherein the memory controller hub transparently ensures durability of updates to persistent pages that are also cached in DRAM.
15. The apparatus of claim 10 , wherein the memory controller hub is configured to, when a read from a memory block is cached in the mirror region of the dynamic random access memory and pressure at the dynamic random access memory is above a threshold, bypassing the mirror region of the dynamic random access memory and accessing the read in the non-volatile memory.
16. The apparatus of claim 10 , wherein the memory controller hub is configured to, when a plurality of pages is cached in the mirror region of the dynamic random access memory, access the plurality of pages in the dynamic random access memory using bank level parallelism, instead of accesses to the non-volatile memory.
17. The apparatus of claim 10 , wherein the memory controller hub is configured to implement multi-queue page eviction based on a least recently used algorithm wherein, when a threshold to be mirrored is reached, M least recently used queues of block descriptors are defined wherein each descriptor comprises a block number, a reference counter and a logical expiration time, wherein a page is cached in the mirror region of the dynamic random access memory using the memory controller hub to both write the page directly to the mirror region of the dynamic random access memory and concurrently mirror the page to the non-volatile memory, to keep hot pages in the mirror region of the dynamic random access memory.
18. An apparatus for architectural support of hybrid memory system persistent applications, the apparatus comprising:
a processor chip comprising a core, a cache, and a memory controller hub;
a non-volatile memory coupled to the processor chip; and
a dynamic random access memory coupled to the processor chip, the dynamic random access memory comprising a mirror mapping table and a mirror region,
wherein the dynamic random access memory caches at least fraction of data stored in the non-volatile memory in the mirror region of the dynamic random access memory,
wherein the memory controller hub is configured to, when an update to the dynamic random access memory is cached in the mirror region of the dynamic random access memory, using the memory controller hub to both write the update directly to the mirror region of the dynamic random access memory and concurrently mirror the update to the non-volatile memory to provide coherent persistent durability of the update,
wherein the mirror mapping table of the dynamic random access memory comprises a hardware managed table including for each mirrored page a group ID, a TAG (non-volatile memory page address) and a dynamic random access memory address.
19. A computer program product for architectural support of hybrid memory system persistent applications, the computer program product comprising:
a non-transitory computer readable storage media; and
program code, stored on the computer readable storage media, for caching at least a fraction of data stored in a non-volatile memory in a mirror region of a dynamic random access memory, the dynamic random access memory comprising a mirror mapping table comprising a hardware managed table,
wherein a memory controller hub of a processor chip coupled to both the non-volatile memory and the dynamic random access memory is configured to, when an update to the dynamic access random access memory is cached in the mirror region of the dynamic random access memory, use the memory controller hub to both write the update directly to the mirror region of the dynamic random access memory and concurrently mirror the update to the non-volatile memory providing coherent persistent durability of the update,
wherein the hardware managed table includes for each mirrored page a group ID, a TAG (non-volatile memory page address) and a dynamic random access memory address.
20. The computer program product of claim 19 , when a read from the dynamic random access memory is cached in the mirror region of the dynamic random access memory, use the memory controller hub to serve the read directly from the mirror region of the dynamic random access memory.
21. The computer program product of claim 19 , when a second update to the dynamic random access memory is not cached in the mirror region of the dynamic random access memory, not concurrently mirroring the update to the non-volatile memory.
22. The computer program product of claim 19 , wherein the memory controller hub supports both memory mode and application direct mode.
23. The computer program product of claim 19 , wherein the memory controller hub transparently ensures durability of updates to persistent pages that are also cached in DRAM.
24. The computer program product of claim 19 , wherein the memory controller hub is configured to, when a read from a memory block is cached in the mirror region of the dynamic random access memory and pressure at the dynamic random access memory is above a threshold, bypassing the mirror region of the dynamic random access memory and accessing the read in the non-volatile memory.
25. The computer program product of claim 19 , wherein the memory controller hub is configured to, when a plurality of pages is cached in the mirror region of the dynamic random access memory, access the plurality of pages in the dynamic random access memory using bank level parallelism, instead of accesses to the non-volatile memory.
26. The computer program product of claim 19 , wherein the memory controller hub is configured to implement multi-queue page eviction based on a least recently used algorithm wherein, when a threshold to be mirrored is reached, M least recently used queues of block descriptors are defined wherein each descriptor comprises a block number, a reference counter and a logical expiration time, wherein a page is cached in the mirror region of the dynamic random access memory using the memory controller hub to both write the page directly to the mirror region of the dynamic random access memory and concurrently mirror the page to the non-volatile memory, to keep hot pages in the mirror region of the dynamic random access memory.
27. A computer program product for architectural support of hybrid memory system persistent applications, the computer program product comprising:
a non-transitory computer readable storage media; and
program code, stored on the computer readable storage media, for caching at least a fraction of data stored in a non-volatile memory in a mirror region of a dynamic random access memory,
wherein a memory controller hub of a processor chip coupled to both the non-volatile memory and the dynamic random access memory is configured to, when an update to the dynamic random access memory is cached in the mirror region of the dynamic random access memory, use the memory controller hub to both write the update directly to the mirror region of the dynamic random access memory and concurrently mirror the update to the non-volatile memory to provide coherent persistent durability of the update,
wherein a mirror mapping table of the dynamic random access memory comprises a hardware managed table including for each mirrored page a group ID, a TAG (non-volatile memory page address) and a dynamic random access memory address.