Memory system and operating method thereof

1. A memory system comprising:

a memory device including a main memory and a cache memory that includes a plurality of cache lines for caching data stored in the main memory, wherein each of the cache lines includes cache data, a valid bit indicating whether or not the corresponding cache data is valid, and a loading bit indicating whether or not read data of the main memory is being loaded; and

a memory controller suitable for scheduling an operation of the memory device with reference to the valid bits and the loading bits, wherein the memory controller manages the loading bit and the valid bit not to be set simultaneously.

2. The memory system of claim 1 , wherein, when the loading bit of a cache-hit cache line, which corresponds to an address of the read data, is set during a read operation, the memory controller waits until the read data is stored in the cache-hit cache line, and then releases the loading bit, sets the valid bit, and outputs the cache data of the cache-hit cache line.

3. The memory system of claim 1 , wherein, when the valid bit of a cache-hit cache line, which corresponds to an address of the read data, is set during a read operation, the memory controller outputs the cache data of the cache-hit cache line.

4. The memory system of claim 1 , wherein, when the loading bit of a cache line, which corresponds to an address of select data to be stored therein, is set during a write operation, the memory controller stores write data as the cache data of the cache-hit cache line, sets the valid bit, and releases the loading bit, and discards the read data when the read data reaches the cache-hit cache line.

5. The memory system of claim 1 , wherein, when the valid bit of a cache line, which corresponds to an address of write data to be stored therein, is set during a write operation, the memory controller stores the write data as the cache data of the cache-hit cache line, and maintains the set state of the valid bit.

6. The memory system of claim 1 , wherein each of the cache lines further includes a tag address designating a storage location of the corresponding cache data,

wherein the memory controller searches for a cache line, which corresponds to an address of select data to be stored therein, based on the tag address in each of the cache lines.

7. The memory system of claim 1 , wherein each of the cache lines further includes a dirty bit indicating whether there is a discrepancy between the corresponding cache data and the data of the main memory.

8. A memory system comprising:

a nonvolatile memory device;

a volatile memory device including a plurality of cache lines for caching data stored in the nonvolatile memory device, wherein each of the cache lines includes cache data, a tag address, a valid bit indicating whether or not the corresponding cache data is valid, a dirty bit indicating whether there is a discrepancy between the corresponding cache data and the data of the nonvolatile memory device, and a loading bit indicating whether or not read data of the nonvolatile memory device is being loaded; and

a memory controller suitable for scheduling an operation of the volatile memory device with reference to the valid bits, the dirty bits and the loading bits, wherein the memory controller manages the loading bit and the valid bit not to be set simultaneously.

9. The memory system of claim 8 , wherein the memory controller searches for a cache line, which corresponds to an address of select data to be stored therein, based on the tag address.

10. The memory system of claim 9 , wherein, when the loading bit of the cache-hit cache line is set during a read operation, the memory controller waits until the read data is stored in the cache-hit cache line, and then releases the loading bit, sets the valid bit, and outputs the cache data of the cache-hit cache line.

11. The memory system of claim 9 , wherein, when the valid bit of the cache-hit cache line is set during a read operation, the memory controller outputs the cache data of the cache-hit cache line.

12. The memory system of claim 9 , wherein, when the loading bit of the cache-hit cache line is set during a write operation, the memory controller stores write data as the cache data of the cache-hit cache line, sets the dirty bit and the valid bit, and releases the loading bit, and discards the read data when the read data reaches the cache-hit cache line.

13. The memory system of claim 9 , wherein, when the valid bit of the cache-hit cache line is set during a write operation, the memory controller stores write data as the cache data of the cache-hit cache line, sets the dirty bit, and maintains the set state of the valid bit.

14. An operating method of a memory system, comprising:

providing a memory device including a main memory and a cache memory that includes a plurality of cache lines for caching data stored in the main memory, wherein each of the cache lines includes cache data, a valid bit indicating whether or not the corresponding cache data is valid, and a loading bit indicating whether or not read data of the main memory is being loaded;

checking whether or not the loading bit of a cache line, which corresponds to an address of select data to be stored therein, is set when a read request is received from a host; and

managing the loading bit and the valid bit not to be set simultaneously by releasing the loading bit while setting the valid bit, and outputting the cache data of the cache-hit cache line after waiting until the read data is stored in the cache-hit cache line, when the loading bit is set.

15. The operating method of claim 14 , further comprising:

outputting the cache data of the cache line when the loading bit of the cache-hit cache line is released and the valid bit is set in response to the read request.

16. The operating method of claim 14 , wherein each of the cache lines further includes a dirty bit indicating a discrepancy between the corresponding cache data and the data of the main memory.

17. The operating method of claim 16 , further comprising:

checking whether or not the loading bit of the cache-hit cache line is set when a write request is received from the host;

storing write data as the cache data of the cache line, setting the dirty bit and the valid bit, and releasing the loading bit, when the loading bit is set; and

discarding the read data when the read data reaches the cache line.

18. The operating method of claim 17 , further comprising:

storing the write data as the cache data of the cache line, setting the dirty bit, and maintaining a set state of the valid bit, when the loading bit of the cache-hit cache line is released and the valid bit is set in response to the write request.

19. The operating method of claim 16 , wherein each of the cache lines further includes a tag address designating a storage location of the corresponding cache data,

wherein the operating method further comprises:

searching for the cache-hit cache line based on the tag address in each of the cache lines.

20. The operating method of claim 19 , further comprising:

searching for an empty cache line based on the valid bit, the dirty bit and the loading bit, when the cache-hit cache line is not found; and

obtaining an empty cache line according to a cache replacement policy when the empty cache line is not found.

21. The operating method of claim 20 , further comprising:

when the cache-hit cache line is not found in response to the read request,

requesting the read data from the main memory and setting the loading bit; and

releasing the loading bit, setting the valid bit, and outputting cache data of the obtained cache line, after waiting until the read data is stored in the obtained cache line.

22. The operating method of claim 20 , further comprising:

storing write data as the cache data of the obtained cache line and setting the dirty bit and the valid bit of the obtained cache line, when the cache-hit cache line is not found in response to a write request.

23. The operating method of claim 22 , further comprising:

writing back the cache data of the cache line in which the dirty bit is set to the main memory and releasing the dirty bit.