Phase-change memory and method of forming same

1. A method comprising:

forming a first dielectric layer over a substrate;

forming a first conductive feature in the first dielectric layer;

forming a second dielectric layer over the first dielectric layer and the first conductive feature;

forming an opening in the second dielectric layer, the opening exposing a topmost surface of the first conductive feature;

filling the opening with a first conductive material to form a bottom electrode in the second dielectric layer;

depositing a phase-change material over the second dielectric layer and the bottom electrode;

depositing a first buffer material over the phase-change material;

depositing a second conductive material over the first buffer material;

performing a patterning process to remove a portion of the phase-change material, a portion of the first buffer material and a portion of the second conductive material, and to expose a topmost surface of the second dielectric layer, wherein a remaining portion of the phase-change material forms a phase-change layer, a remaining portion of the first buffer material forms a first buffer layer, and a remaining portion of the second conductive material forms a top electrode; and

forming a third dielectric layer over the second dielectric layer, the third dielectric layer surrounding the first buffer layer, the phase-change layer and the top electrode.

2. The method of claim 1 , further comprising, before depositing the phase-change material, depositing a second buffer material over the second dielectric layer and the bottom electrode.

3. The method of claim 2 , wherein performing the patterning process further comprises removing a portion of the second buffer material, a remaining portion of the second buffer material forming a second buffer layer, the second buffer layer and the first buffer layer having a same width.

4. The method of claim 1 , further comprising recessing the bottom electrode below the topmost surface of the second dielectric layer to form a recess.

5. The method of claim 4 , further comprising filling the recess with a second buffer material to form a second buffer layer in the recess, a width of the second buffer layer being less than a width of the first buffer layer.

6. The method of claim 1 , further comprising:

forming a fourth dielectric layer over the third dielectric layer and the top electrode; and

forming a second conductive feature in the fourth dielectric layer, the second conductive feature being in electrical contact with the top electrode.

7. A method comprising:

forming a first dielectric layer over a substrate;

forming a first conductive feature in the first dielectric layer;

forming a second dielectric layer over the first dielectric layer and the first conductive feature;

forming an opening in the second dielectric layer, the opening exposing a topmost surface of the first conductive feature;

filling the opening with a first conductive material to form a bottom electrode in the second dielectric layer;

recessing the bottom electrode below a top surface of the second dielectric layer to form a recess;

depositing a first buffer material in the recess to form a first buffer layer, a top surface of the first buffer layer being substantially level with the top surface of the second dielectric layer;

depositing a phase-change material over the second dielectric layer and the first buffer layer;

depositing a second conductive material over the phase-change material;

performing a patterning process to remove a portion of the phase-change material and a portion of the second conductive material, and to expose the top surface of the second dielectric layer, wherein a remaining portion of the phase-change material forms a phase-change layer and a remaining portion of the second conductive material forms a top electrode; and

forming a third dielectric layer over the second dielectric layer, the third dielectric layer surrounding the phase-change layer and the top electrode.

8. The method of claim 7 , further comprising, before depositing the second conductive material over the phase-change material, depositing a second buffer material over the phase-change material.

9. The method of claim 8 , wherein the patterning process further removes a portion of the second buffer material, a remaining portion of the second buffer material forming a second buffer layer.

10. The method of claim 9 , wherein the first buffer layer and the second buffer layer comprise a same material.

11. The method of claim 9 , wherein the first buffer layer and the second buffer layer comprise different materials.

12. The method of claim 7 , wherein the third dielectric layer is in physical contact with sidewalls of the phase-change layer and sidewall of the top electrode, and wherein a top surface of the top electrode is substantially level with a top surface of the third dielectric layer.

13. The method of claim 7 , wherein the bottom electrode and the top electrode comprise different conductive materials.

14. A method comprising:

forming a first interconnect structure over a substrate;

forming a first dielectric layer over the first interconnect structure;

forming a bottom electrode within the first dielectric layer;

forming a first buffer layer over the bottom electrode;

forming a phase-change layer over the first buffer layer, the phase-change layer being in physical contact with a top surface of the first dielectric layer, wherein a width of the phase-change layer is greater than a width of the bottom electrode;

forming a top electrode over the phase-change layer; and

forming a second dielectric layer over the first dielectric layer, wherein the second dielectric layer is in physical contact with sidewalls of the phase-change layer and sidewalls of the top electrode.

15. The method of claim 14 , wherein the width of the phase-change layer is same as a width of the top electrode.

16. The method of claim 14 , further comprising forming a second buffer layer between the phase-change layer and the top electrode.

17. The method of claim 16 , wherein the width of the phase-change layer is same as a width of the second buffer layer.

18. The method of claim 14 , wherein with the top surface of the first dielectric layer is substantially level with a top surface of the first buffer layer.

19. The method of claim 14 , wherein the bottom electrode and the top electrode comprise a same conductive material.

20. The method of claim 14 , further comprising forming a second interconnect structure over the second dielectric layer and the top electrode.