Systems and methods for performing matrix compress and decompress instructions
Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.
1. A processor comprising:
fetch circuitry to fetch a single compress instruction having a format with fields to specify an opcode, a location of a decompressed source matrix, and a location of a compressed destination matrix;
decode circuitry to decode the fetched single compress instruction; and
execution circuitry, responsive to the decoded single compress instruction, to:
generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by packing non-zero-valued elements together;
store a matrix position of each non-zero-valued element in a header; and
store the compressed result to the specified compressed destination matrix.
2. The processor of claim 1 , wherein the execution circuitry is further to perform an arithmetic or logical operation on elements of the compressed result before storing the compressed result to the specified compressed destination matrix.
3. The processor of claim 1 , wherein the specified decompressed source and compressed destination matrices are each located in any of a collection of floating-point registers, a collection of vector registers, a collection of tile registers, and memory.
4. The processor of claim 1 , wherein:
the fetch circuitry is further to fetch a single decompress instruction specifying locations of compressed source and decompressed destination matrices, wherein the compressed result is specified as the compressed source matrix;
the decode circuitry is further to decode the fetched single decompress instruction; and
the execution circuitry is further to respond to the decoded single decompress instruction by writing each of the non-zero-valued elements of the specified compressed source matrix to its associated position within the specified decompressed destination matrix, the associated position being determined by the header.
5. The processor of claim 1 , wherein the header comprises a multi-bit value having a bit for each element position of the specified decompressed source matrix, the bit to identify non-zero-valued elements of the decompressed source matrix.
6. A processor comprising:
fetch circuitry to fetch a single decompress instruction whose format has fields to specify an opcode, a location of a compressed source matrix, and a location of a decompressed destination matrix;
decode circuitry to decode the fetched single decompress instruction; and
execution circuitry, responsive to the decoded single decompress instruction, to:
generate a decompressed result according to a decompress algorithm by, when the specified compressed source matrix comprises packed non-zero-valued elements, copying each element of the specified source matrix to its associated position within the specified decompressed destination matrix, the associated position being identified by a header; and
store the decompressed result to the specified decompressed destination matrix.
7. The processor of claim 6 , wherein the execution circuitry is further to perform an arithmetic or logical operation on elements of the decompressed result before storing the decompressed result to the specified decompressed destination matrix.
8. The processor of claim 6 , wherein the specified compressed source and decompressed destination matrices are each located in any of a collection of floating-point registers, a collection of vector registers, a collection of tile registers, and memory.
9. The processor of claim 6 , wherein:
the fetch circuitry is further to fetch a single compress instruction specifying locations of decompressed source and compressed destination matrices; wherein the generated decompressed result is specified as the decompressed source matrix;
the decode circuitry is further to decode the fetched single compress instruction; and
the execution circuitry is further to respond to the decoded single compress instruction according to a compress algorithm by compressing the specified decompressed source matrix by packing non-zero-valued elements together and storing a matrix position of each non-zero-valued element in a header.
10. The processor of claim 6 , wherein the header comprises a multi-bit value having a bit for each element position of the specified decompressed destination matrix, the bit to identify non-zero-valued elements of the decompressed destination matrix.
11. A method comprising:
fetching, using fetch circuitry, a single compress instruction having a format with fields to specify an opcode, a location of a decompressed source matrix, and a location of a compressed destination matrix;
decoding, using decode circuitry, the fetched single compress instruction; and
executing, using execution circuitry, the decoded single compress instruction by:
generating a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by packing non-zero-valued elements together;
storing a matrix position of each non-zero-valued element in a header; and
storing the compressed result to the specified compressed destination matrix.
12. The method of claim 11 , wherein the executing further comprises performing an arithmetic or logical operation on elements of the compressed result before storing the compressed result to the specified compressed destination matrix.
13. The method of claim 11 , wherein the specified decompressed source and compressed destination matrices are each located in any of a collection of floating-point registers, a collection of vector registers, a collection of tile registers, and memory.
14. The method of claim 11 , further comprising:
fetching, using the fetch circuitry, a single decompress instruction specifying locations of compressed source and decompressed destination matrices, wherein the compressed result is specified as the compressed source matrix;
decoding, using the decode circuitry, the fetched single decompress instruction; and
executing, using the execution circuitry, the decoded single decompress instruction by writing each of the non-zero-valued elements of the specified compressed source matrix to its associated position within the specified decompressed destination matrix, the associated position being determined by the header.
15. The method of claim 11 , wherein the header comprises a multi-bit value having a bit for each element position of the specified decompressed source matrix, the bit to identify non-zero-valued elements of the decompressed source matrix.
16. A method comprising:
fetching, using fetch circuitry, a single decompress instruction whose format has fields to specify an opcode, a location of a compressed source matrix, and a location of a decompressed destination matrix;
decoding, using decode circuitry, the fetched single decompress instruction; and
executing, using execution circuitry, the decoded single decompress instruction by:
generating a decompressed result according to a decompress algorithm by, when the specified compressed source matrix comprises packed non-zero-valued elements, copying each element of the specified source matrix to its associated position within the specified decompressed destination matrix, the associated position being identified by a header; and
storing the decompressed result to the specified decompressed destination matrix.
17. The method of claim 16 , wherein the executing further comprises performing an arithmetic or logical operation on elements of the decompressed result before storing the decompressed result to the specified decompressed destination matrix.
18. The method of claim 16 , wherein the specified compressed source and decompressed destination matrices are each located in any of a collection of floating-point registers, a collection of vector registers, a collection of tile registers, and memory.
19. The method of claim 16 , further comprising:
fetching, using the fetch circuitry, a single compress instruction specifying locations of decompressed source and compressed destination matrices; wherein the generated decompressed result is specified as the decompressed source matrix;
decoding, using the decode circuitry, the fetched single compress instruction; and
executing, using the execution circuitry, the decoded single compress instruction according to a compress algorithm by compressing the specified decompressed source matrix by packing non-zero-valued elements together and storing a matrix position of each non-zero-valued element in a header.
20. The method of claim 16 , wherein the header comprises a multi-bit value having a bit for each element position of the specified decompressed destination matrix, the bit to identify non-zero-valued elements of the decompressed destination matrix.