Systems and methods for performing matrix compress and decompress instructions
Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.
1. A processor comprising:
fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices;
decode circuitry to decode the fetched compress instructions; and
execution circuitry, responsive to the decoded compress instruction, to:
generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and
store the compressed result to the specified compressed destination matrix.
2. The processor of claim 1 , wherein the execution circuitry is further to perform an arithmetic or logical operation on elements of the compressed result before storing the compressed result to the specified compressed destination matrix.
3. The processor of claim 1 , wherein the specified decompressed source and compressed destination matrices are each located in any of a collection of floating-point registers, a collection of vector registers, a collection of tile registers, and memory.
4. The processor of claim 1 , wherein:
the fetch circuitry is further to fetch a decompress instruction specifying locations of compressed source and decompressed destination matrices, wherein the compressed result is specified as the compressed source matrix, the compressed result having been generated by packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in the header;
the decode circuitry is further to decode the fetched decompress instruction; and
the execution circuitry is further to respond to the decoded decompress instruction by writing each of the non-zero-valued elements of the specified compressed source matrix to its associated position within the specified decompressed destination matrix, the associated position being determined by the header.
5. The processor of claim 1 , wherein when the compressed result is generated by packing non-zero-valued elements together, the header comprises a multi-bit value having a bit for each element position of the specified decompressed source matrix, the bit to identify non-zero-valued elements of the decompressed source matrix.
6. The processor of claim 1 , wherein when the compressed result is generated by using fewer bits to represent one or more elements, the header comprises a multi-bit value having a bit for each element position of the specified decompressed source matrix, the bit to identify elements of the compressed result being represented by fewer bits.
7. The processor of claim 1 , wherein when the execution circuitry is to generate the compressed result by using fewer bits to represent one or more elements, the one or more elements are replaced with a pointer to a dictionary of values, the pointer using fewer bits than the specified uncompressed source matrix element.
8. A processor comprising:
fetch circuitry to fetch a decompress instruction whose format has fields to specify an opcode and locations of compressed source and decompressed destination matrices;
decode circuitry to decode the fetched decompress instructions; and
execution circuitry, responsive to the decoded decompress instruction, to:
generate a decompressed result according to a decompress algorithm by, when the specified compressed source matrix comprises packed non-zero-valued elements, copying each element of the specified source matrix to its associated position within the specified decompressed destination matrix, the associated position being identified by a multi-bit header having one bit per element of the specified decompressed destination matrix, with bits corresponding to non-zero-valued elements being set; and
store the decompressed result to the specified decompressed destination matrix.
9. The processor of claim 8 , wherein the execution circuitry is further to perform an arithmetic or logical operation on elements of the decompressed result before storing the decompressed result to the specified decompressed destination matrix.
10. The processor of claim 8 , wherein the specified compressed source and decompressed destination matrices are each located in any of a collection of floating-point registers, a collection of vector registers, a collection of tile registers, and memory.
11. The processor of claim 8 , wherein:
the fetch circuitry is further to fetch a compress instruction specifying locations of decompressed source and compressed destination matrices; wherein the generated decompressed result is specified as the decompressed source matrix;
the decode circuitry is further to decode the fetched compress instruction; and
the execution circuitry is further to respond to the decoded compress instruction according to a compress algorithm by compressing the specified compressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits.
12. The processor of claim 8 , wherein when the execution circuitry is to generate the compressed result by using fewer bits to represent one or more elements, the one or more elements are replaced with a pointer to a dictionary of values, the pointer using fewer bits than the specified uncompressed source matrix element.
13. A method to be performed by a processor, the processor to:
fetch, using fetch circuitry, a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices;
decode, using decode circuitry, the fetched compress instructions; and
respond, using execution circuitry, to the decoded compress instruction, by:
generating a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and
storing the compressed result to the specified compressed destination matrix.
14. The method of claim 13 , wherein the execution circuitry is further to perform an arithmetic or logical operation on elements of the compressed result before storing the compressed result to the specified compressed destination matrix.
15. The method of claim 13 , wherein the specified decompressed source and compressed destination matrices are each located in any of a collection of floating-point registers, a collection of vector registers, a collection of tile registers, and memory.
16. The method of claim 13 , wherein:
the fetch circuitry is further to fetch a decompress instruction specifying locations of compressed source and decompressed destination matrices, wherein the compressed result is specified as the compressed source matrix, the compressed result having been generated by packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in the header;
the decode circuitry is further to decode the fetched decompress instruction; and
the execution circuitry is further to respond to the decoded decompress instruction by writing each of the non-zero-valued elements of the specified compressed source matrix to its associated position within the specified decompressed destination matrix, the associated position being determined by the header.
17. The method of claim 13 , wherein when the compressed result is generated by packing non-zero-valued elements together, the header comprises a multi-bit value having a bit for each element position of the specified decompressed source matrix, the bit to identify non-zero-valued elements of the decompressed source matrix.
18. A non-transitory computer-readable medium containing instructions, when executed by a processor, cause the processor to:
fetch, using fetch circuitry, a decompress instruction whose format has fields to specify an opcode and locations of compressed source and decompressed destination matrices;
decode, using decode circuitry, the fetched decompress instructions; and
respond, using execution circuitry, to the decoded decompress instruction, to:
generate a decompressed result according to a decompress algorithm by, when the specified compressed source matrix comprises packed non-zero-valued elements, copying each element of the specified source matrix to its associated position within the specified decompressed destination matrix, the associated position being identified by a multi-bit header having one bit per element of the specified decompressed destination matrix, with bits corresponding to non-zero-valued elements being set; and
store the decompressed result to the specified decompressed destination matrix.
19. The non-transitory computer-readable medium of claim 18 , wherein the execution circuitry is further to perform an arithmetic or logical operation on elements of the decompressed result before storing the decompressed result to the specified decompressed destination matrix.
20. The non-transitory computer-readable medium of claim 18 , wherein:
the fetch circuitry is further to fetch a compress instruction specifying locations of decompressed source and compressed destination matrices; wherein the generated decompressed result is specified as the decompressed source matrix;
the decode circuitry is further to decode the fetched compress instruction; and
the execution circuitry is further to respond to the decoded compress instruction according to a compress algorithm by compressing the specified compressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits.