Granted Patent B2

US 12,282,721 · App. 17/684,451 · Granted Apr 22, 2025

Inventors: Michael Kazda (Poughkeepsie, NY); Sean Michael Carey (Dutchess, NY); Frank J. Musante (Poughkeepsie, NY); Michael Hemsley Wood (Wilmington, DE)

Assignee: International Business Machines Corporation

G06F30/327

Abstract

Claims (78)

1. A computer-implemented method comprising:

determining, by a processor, a netlist for an integrated circuit design, wherein the netlist comprises a design for placement of a plurality of latches within an integrated circuit;

determining a set of timing paths from the netlist, wherein each timing path in the set of timing paths comprises a capture latch and at least one launch latch connected to a same local clock buffer controller through a local clock buffer OR circuit;

calculating a slack value for each timing path in the set of timing paths;

determining one or more candidate timing paths from the set of timing paths, wherein the one or more candidate timing paths have a slack value below a threshold slack value;

calculating a score for each candidate timing path of the one or more candidate timing paths based on a count of a number of launch latch and capture latch pairs within the candidate timing path;

adjusting an interconnect for a first candidate timing path from the one or more candidate timing paths based on the first candidate timing path having a highest score of all scores for the one or more candidate timing path; and

generating an updated netlist based on the adjusting the interconnect for the first candidate timing path.

2. The computer-implemented method of claim 1 , wherein adjusting the interconnect for the first candidate timing path comprises:

disconnecting a first local clock buffer OR circuit from a first local clock buffer controller in the first candidate timing path; and

connecting the first local clock buffer OR circuit to a second local clock buffer controller.

3. The computer-implemented method of claim 2 , wherein the second local clock buffer is a nearest local clock buffer controller to the first local clock buffer OR circuit.

4. The computer-implemented method of claim 1 , further comprising:

determining a second set of timing paths from the updated netlist;

calculating a second slack value for each timing path in the second set of timing paths;

determining one or more candidate timing paths from the second set of timing paths, wherein the one or more candidate timing paths have a slack value below the threshold slack value;

calculating a second score for each candidate timing path of the one or more candidate timing paths based on a count of a number of launch latch and capture latch pairs within the candidate timing path;

adjusting an interconnect for a second candidate timing path from the one or more candidate timing paths based on the second candidate timing path having a highest score of all scores for the one or more candidate timing path; and

updating the updated netlist based on the adjusting of the interconnect for the second candidate timing path.

5. The computer-implemented method of claim 1 , further comprising:

iteratively calculating a score for each candidate timing path of the one or more candidate timing paths until a total score for the netlist is less than a total score threshold, wherein the total score comprises a summation of each score for each candidate timing path.

6. The computer-implemented method of claim 1 , wherein calculating the slack value for each timing path in the set of timing paths comprises:

determining a desired timing for the timing path based on a timing metric for the timing path; and

calculating an actual timing for the timing path, wherein the slack value comprises a difference between the actual timing and the desired timing.

7. The computer-implemented method of claim 1 , further comprising:

causing, by the processor, the fabrication of the integrated circuit design based on the updated netlist.

8. A system comprising:

a memory having computer readable instructions; and

one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:

determining, by a processor, a netlist for an integrated circuit design, wherein the netlist comprises a design for placement of a plurality of latches within an integrated circuit;

determining a set of timing paths from the netlist, wherein each timing path in the set of timing paths comprise a capture latch and at least one launch latch connected to a same local clock buffer controller through a local clock buffer OR circuit;

calculating a slack value for each timing path in the set of timing paths;

determining one or more candidate timing paths from the set of timing paths, wherein the one or more candidate timing paths have a slack value below a threshold slack value;

calculating a score for each candidate timing path of the one or more candidate timing paths based on a count of a number of launch latch and capture latch pairs within the candidate timing path;

adjusting an interconnect for a first candidate timing path from the one or more candidate timing paths based on the first candidate timing path having a highest score of all scores for the one or more candidate timing path; and

generating an updated netlist based on the adjusting the interconnect for the first candidate timing path.

9. The system of claim 8 , wherein adjusting the interconnect for the first candidate timing path comprises:

disconnecting a first local clock buffer OR circuit from a first local clock buffer controller in the first candidate timing path;

connecting the first local clock buffer OR circuit to a second local clock buffer controller.

10. The system of claim 9 , wherein the second local clock buffer is a nearest local clock buffer controller to the first local clock buffer OR circuit.

11. The system of claim 8 , wherein the operations further comprise:

determining a second set of timing paths from the updated netlist;

calculating a second slack value for each timing path in the second set of timing paths;

determining one or more candidate timing paths from the second set of timing paths, wherein the one or more candidate timing paths have a slack value below the threshold slack value;

calculating a second score for each candidate timing path of the one or more candidate timing paths based on a count of a number of launch latch and capture latch pairs within the candidate timing path;

adjusting an interconnect for a second candidate timing path from the one or more candidate timing paths based on the second candidate timing path having a highest score of all scores for the one or more candidate timing path; and

updating the updated netlist based on the adjusting of the interconnect for the second candidate timing path.

12. The system of claim 8 , wherein the operations further comprise:

iteratively calculating a score for each candidate timing path of the one or more candidate timing paths until a total score for the netlist is less than a total score threshold, wherein the total score comprises a summation of each score for each candidate timing path.

13. The system of claim 8 , wherein calculating the slack value for each timing path in the set of timing paths comprises:

determining a desired timing for the timing path based on a timing metric for the timing path; and

calculating an actual timing for the timing path, wherein the slack value comprises a difference between the actual timing and the desired timing.

14. The system of claim 8 , wherein the operations further comprise:

causing the fabrication of the integrated circuit design based on the updated netlist.

15. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising:

determining, by a processor, a netlist for an integrated circuit design, wherein the netlist comprises a design for placement of a plurality of latches within an integrated circuit;

determining a set of timing paths from the netlist, wherein each timing path in the set of timing paths comprise a capture latch and at least one launch latch connected to a same local clock buffer controller through a local clock buffer OR circuit;

calculating a slack value for each timing path in the set of timing paths;

determining one or more candidate timing paths from the set of timing paths, wherein the one or more candidate timing paths have a slack value below a threshold slack value;

calculating a score for each candidate timing path of the one or more candidate timing paths based on a count of a number of launch latch and capture latch pairs within the candidate timing path;

adjusting an interconnect for a first candidate timing path from the one or more candidate timing paths based on the first candidate timing path having a highest score of all scores for the one or more candidate timing paths; and

generating an updated netlist based on the adjusting the interconnect for the first candidate timing path.

16. The computer program product of claim 15 , wherein adjusting the interconnect for the first candidate timing path comprises:

disconnecting a first local clock buffer OR circuit from a first local clock buffer controller in the first candidate timing path;

connecting the first local clock buffer OR circuit to a second local clock buffer controller.

17. The computer program product of claim 16 , wherein the second local clock buffer is a nearest local clock buffer controller to the first local clock buffer OR circuit.

18. The computer program product of claim 15 , wherein the operations further comprise:

determining a second set of timing paths from the updated netlist;

calculating a second slack value for each timing path in the second set of timing paths;

determining one or more candidate timing paths from the second set of timing paths, wherein the one or more candidate timing paths have a slack value below the threshold slack value;

calculating a second score for each candidate timing path of the one or more candidate timing paths based on a count of a number of launch latch and capture latch pairs within the candidate timing path;

adjusting an interconnect for a second candidate timing path from the one or more candidate timing paths based on the second candidate timing path having a highest score of all scores for the one or more candidate timing paths; and

updating the updated netlist based on the adjusting the interconnect for the second candidate timing path.

19. The computer program product of claim 15 , wherein the operations further comprise:

iteratively calculating a score for each candidate timing path of the one or more candidate timing paths until a total score for the netlist is less than a total score threshold, wherein the total score comprises a summation of each score for each candidate timing path.

20. The computer program product of claim 15 , wherein calculating the slack value for each timing path in the set of timing paths comprises:

determining a desired timing for the timing path based on a timing metric for the timing path; and

calculating an actual timing for the timing path, wherein the slack value comprises a difference between the actual timing and the desired timing.

Assignments (1)

Continuity (1)

References Cited (12)