Placement aware functional engineering change order extraction
A computer implemented method for designing an integrated circuit includes receiving a netlist. The method also includes receiving physical layout information related to an integrated circuit based on the on the netlist and receiving an engineering change order (ECO) that changes at least one logical component of the physical layout. The method further includes forming two or more possible solutions to achieve the ECO, ranking the two or more possible solutions based on two or more factors and selecting the highest ranked solution.
1. A computer implemented method for designing an integrated circuit, the method comprising:
receiving a netlist;
receiving physical layout information related to an integrated circuit based on the netlist;
receiving an engineering change order (ECO) that adds at least one logic gate to the physical layout;
forming two or more possible solutions to achieve the ECO;
ranking the two or more possible solutions based on two or more factors to obtain a highest ranked solution; and
selecting the highest ranked solution;
wherein ranking includes determining that a tie between solutions exists and the tie is broken based, in order, on scores for routing congestion, timing, placement density and cell density.
2. The method of claim 1 , wherein the physical layout information includes layout and routing information.
3. The method of claim 1 , wherein forming includes extracting one or both of a cell density map and a congestion map from the physical layout information.
4. The method of claim 3 , wherein the ranking includes scoring the solutions based on a comparison to one or more of the cell density map and the congestion map.
5. The method of claim 1 , wherein the ranking includes scoring the solutions based on a comparison to a timing analysis of the netlist.
6. A computer program product for implementing designing an integrated circuit, the computer program product comprising:
a tangible storage medium readable by a processing circuit and storing instructions which, when executed by the processing circuit performs a method comprising:
receiving a netlist;
receiving physical layout information related to an integrated circuit based on the netlist;
receiving an engineering change order (ECO) that adds at least one logic gate to the physical layout;
forming two or more possible solutions to achieve the ECO;
ranking the two or more possible solutions based on two or more factors to obtain a highest ranked solution; and
selecting the highest ranked solution;
wherein ranking includes determining that a tie between solutions exists and, the tie is broken based, in order, on scores for routing congestion, timing, placement density and cell density.
7. The computer program product of claim 6 , wherein the physical layout information includes layout and routing information.
8. The computer program product of claim 6 , wherein forming includes extracting one or both of a cell density map and a congestion map from the physical layout information.
9. The computer program product of claim 8 , wherein the ranking includes scoring the solutions based on a comparison to one or more of the cell density map and the congestion map.
10. The computer program product of claim 6 , wherein the ranking includes scoring the solutions based on a comparison to a timing analysis of the netlist.