Miniature field plate T-gate and method of fabricating the same
A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer; and forming a tri-layer gate having a gate foot in the first opening, the gate foot having a first width, a gate neck extending from the gate foot and extending for a length over the dielectric passivation layer on both sides of the first opening, the gate neck having a second width wider than the first width of the gate foot, and a gate head extending from the gate neck, the gate head having a third width wider than the second width of the gate neck.
1. A transistor having a gate with a mini field plate comprising:
a substrate;
an epitaxy layer on the substrate;
a dielectric passivation layer on the epitaxy layer;
a first opening in the dielectric passivation layer;
a tri-layer gate, the tri-layer gate comprising:
a gate foot in the first opening, the gate foot having a first width;
a gate neck extending from the gate foot and extending for a length over the dielectric passivation layer on both sides of the first opening, the gate neck having a second width wider than the first width of the gate foot; and
a gate head extending from the gate neck, the gate head having a third width wider than the second width of the gate neck;
wherein the gate head having a third width wider than the second width of the gate neck comprises:
a third field plate on one side of the gate neck; and
a fourth field plate on another side of the gate neck;
wherein the third field plate is separated from the dielectric passivation layer by an air gap; and
wherein the fourth field plate is separated from the dielectric passivation layer by an air gap;
the transistor comprising a dielectric over the tri-layer gate.
2. The transistor of claim 1 further comprising ohmic contacts.
3. The transistor of claim 1 wherein the substrate comprises GaN, sapphire, silicon carbide (SiC), silicon (Si), GaAs, InP, or InSb.
4. The transistor of claim 1 wherein the epitaxy layer comprises an AlGaN barrier layer.
5. The transistor of claim 1 wherein the transistor comprises a high electron mobility transistor.
6. The transistor of claim 1 :
wherein the gate neck extending for a length over the dielectric passivation layer on both sides of the first opening comprises:
a first mini field plate on one side of the first opening; and
a second mini field plate on another side of the first opening.
7. The transistor of claim 6 :
wherein the first mini field plate has a width of 10 nanometers to 40 nanometers; and
wherein the second mini field plate has a width of 10 nanometers to 40 nanometers.
8. The transistor of claim 6 :
wherein the height of the first mini field plate above the epitaxy layer is 5 nanometers to 75 nanometers; and
wherein the height of the second mini field plate above the epitaxy layer is 5 nanometers to 75 nanometers.
9. The transistor of claim 1 wherein the dielectric passivation layer has a thickness of 5 nanometers to 75 nanometers.
10. The transistor of claim 1 wherein the gate foot has a width of 40 nanometers or less.