Apparatuses, methods, and systems for hashing instructions
Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.
1. A processor comprising:
a decode circuit to decode a first instruction, the first instruction comprising a plurality of fields to specify a first vector register and a second vector register, the first vector register to store a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, the second vector register to store a fifth 64-bit data element and a sixth 64-bit data element; and
an execution circuit coupled with the decode circuit, the execution circuit to perform operations corresponding to the first instruction, including to:
generate a result, the result to include:
a first 64-bit result element that is to be equivalent to the first 64-bit data element added to a value equivalent to the fifth 64-bit data element rotated right by nineteen bits exclusive OR'd (XOR'd) with the fifth 64-bit data element rotated right by sixty-one bits XOR'd with the fifth 64-bit data element shifted right by six bits;
a second 64-bit result element that is to be equivalent to the second 64-bit data element added to a value equivalent to the sixth 64-bit data element rotated right by nineteen bits XOR'd with the sixth 64-bit data element rotated right by sixty-one bits XOR'd with the sixth 64-bit data element shifted right by six bits;
a third 64-bit result element that is to be equivalent to the third 64-bit data element added to a value equivalent to the first 64-bit result element rotated right by nineteen bits XOR'd with the first 64-bit result element rotated right by sixty-one bits XOR'd with the first 64-bit result element shifted right by six bits; and
a fourth 64-bit result element that is to be equivalent to the fourth 64-bit data element added to a value equivalent to the second 64-bit result element rotated right by nineteen bits XOR'd with the second 64-bit result element rotated right by sixty-one bits XOR'd with the second 64-bit result element shifted right by six bits; and
store the result in the first vector register.
2. The processor of claim 1 , wherein the fifth and sixth 64-bit data elements are message elements according to a SHA512 hashing standard.
3. The processor of claim 1 , wherein the first instruction is one of two instructions to generate four SHA512 messages.
4. The processor of claim 1 , wherein the first 64-bit data element is to be stored in bits [63:0] of the first vector register, the second 64-bit data element is to be stored in bits [127:64] of the first vector register, the third 64-bit data element is to be stored in bits [191:128] of the first vector register, and the fourth 64-bit data element is to be stored in bits [255:192] of the first vector register.
5. The processor of claim 1 , wherein the execution circuit is to store the first 64-bit result element in bits [63:0] of the first vector register, the second 64-bit result element in bits [127:64] of the first vector register, the third 64-bit result element in bits [191:128] of the first vector register, and the fourth 64-bit result element in bits [255:192] of the first vector register.
6. The processor of claim 1 , wherein the first vector register is a 256-bits vector register.
7. The processor of claim 1 , wherein the first vector register is a YMM register.
8. The processor of claim 1 , wherein the processor is a complex instruction set computing (CISC) processor.
9. A method comprising:
decoding a first instruction, the first instruction comprising a plurality of fields specifying a first vector register and a second vector register, the first vector register storing a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, the second vector register storing a fifth 64-bit data element and a sixth 64-bit data element; and
performing operations corresponding to the first instruction, including:
generating a result, the result including:
a first 64-bit result element that is to be equivalent to the first 64-bit data element added to a value equivalent to the fifth 64-bit data element rotated right by nineteen bits exclusive OR'd (XOR'd) with the fifth 64-bit data element rotated right by sixty-one bits XOR'd with the fifth 64-bit data element shifted right by six bits;
a second 64-bit result element that is to be equivalent to the second 64-bit data element added to a value equivalent to the sixth 64-bit data element rotated right by nineteen bits XOR'd with the sixth 64-bit data element rotated right by sixty-one bits XOR'd with the sixth 64-bit data element shifted right by six bits;
a third 64-bit result element that is to be equivalent to the third 64-bit data element added to a value equivalent to the first 64-bit result element rotated right by nineteen bits XOR'd with the first 64-bit result element rotated right by sixty-one bits XOR'd with the first 64-bit result element shifted right by six bits; and
a fourth 64-bit result element that is to be equivalent to the fourth 64-bit data element added to a value equivalent to the second 64-bit result element rotated right by nineteen bits XOR'd with the second 64-bit result element rotated right by sixty-one bits XOR'd with the second 64-bit result element shifted right by six bits; and
storing the result in the first vector register.
10. The method of claim 9 , wherein the first 64-bit data element is to be stored in bits [63:0] of the first vector register, the second 64-bit data element is to be stored in bits [127:64] of the first vector register, the third 64-bit data element is to be stored in bits [191:128] of the first vector register, and the fourth 64-bit data element is to be stored in bits [255:192] of the first vector register.
11. The method of claim 9 , wherein storing the result in the first vector register comprises storing the first 64-bit result element in bits [63:0] of the first vector register, the second 64-bit result element in bits [127:64] of the first vector register, the third 64-bit result element in bits [191:128] of the first vector register, and the fourth 64-bit result element in bits [255:192] of the first vector register.
12. The method of claim 9 , wherein storing the result in the first vector register comprises storing the result in a 256-bits vector register.
13. The method of claim 9 , wherein storing the result in the first vector register comprises storing the result in a YMM register.
14. A system comprising:
a non-transitory machine readable storage medium storing code that when executed by the system causes the system to convert a first instruction of a first instruction set into one or more instructions of a second, different instruction set, the first instruction comprising a plurality of fields to specify a first vector register and a second vector register, the first vector register to store a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, the second vector register to store a fifth 64-bit data element and a sixth 64-bit data element;
a processor coupled with the non-transitory machine readable storage medium, the processor to perform the one or more instructions of the second instruction set to perform operations corresponding to the first instruction, including to:
generate a result, the result to include:
a first 64-bit result element that is to be equivalent to the first 64-bit data element added to a value equivalent to the fifth 64-bit data element rotated right by nineteen bits exclusive OR'd (XOR'd) with the fifth 64-bit data element rotated right by sixty-one bits XOR'd with the fifth 64-bit data element shifted right by six bits;
a second 64-bit result element that is to be equivalent to the second 64-bit data element added to a value equivalent to the sixth 64-bit data element rotated right by nineteen bits XOR'd with the sixth 64-bit data element rotated right by sixty-one bits XOR'd with the sixth 64-bit data element shifted right by six bits;
a third 64-bit result element that is to be equivalent to the third 64-bit data element added to a value equivalent to the first 64-bit result element rotated right by nineteen bits XOR'd with the first 64-bit result element rotated right by sixty-one bits XOR'd with the first 64-bit result element shifted right by six bits; and
a fourth 64-bit result element that is to be equivalent to the fourth 64-bit data element added to a value equivalent to the second 64-bit result element rotated right by nineteen bits XOR'd with the second 64-bit result element rotated right by sixty-one bits XOR'd with the second 64-bit result element shifted right by six bits; and
store the result in a destination.
15. The system of claim 14 , wherein the fifth and sixth 64-bit data elements are message elements according to a SHA512 hashing standard, and wherein the first instruction is one of two instructions to generate four SHA512 messages.
16. The system of claim 14 , wherein the first 64-bit data element is to be stored in bits [63:0] of the first vector register, the second 64-bit data element is to be stored in bits [127:64] of the first vector register, the third 64-bit data element is to be stored in bits [191:128] of the first vector register, and the fourth 64-bit data element is to be stored in bits [255:192] of the first vector register.
17. The system of claim 14 , wherein the processor is to store the first 64-bit result element in bits [63:0] of the destination, the second 64-bit result element in bits [127:64] of the destination, the third 64-bit result element in bits [191:128] of the destination, and the fourth 64-bit result element in bits [255:192] of the destination.
18. The system of claim 14 , wherein the first vector register is a YMM register.
19. A non-transitory machine readable storage medium storing code, including a first instruction, that when executed by a machine causes the machine to perform a method comprising:
decoding the first instruction, the first instruction comprising a plurality of fields specifying a first vector register and a second vector register, the first vector register storing a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, the second vector register storing a fifth 64-bit data element and a sixth 64-bit data element; and
performing operations corresponding to the first instruction, including:
generating a result, the result including:
a first 64-bit result element that is to be equivalent to the first 64-bit data element added to a value equivalent to the fifth 64-bit data element rotated right by nineteen bits exclusive OR'd (XOR'd) with the fifth 64-bit data element rotated right by sixty-one bits XOR'd with the fifth 64-bit data element shifted right by six bits;
a second 64-bit result element that is to be equivalent to the second 64-bit data element added to a value equivalent to the sixth 64-bit data element rotated right by nineteen bits XOR'd with the sixth 64-bit data element rotated right by sixty-one bits XOR'd with the sixth 64-bit data element shifted right by six bits;
a third 64-bit result element that is to be equivalent to the third 64-bit data element added to a value equivalent to the first 64-bit result element rotated right by nineteen bits XOR'd with the first 64-bit result element rotated right by sixty-one bits XOR'd with the first 64-bit result element shifted right by six bits; and
a fourth 64-bit result element that is to be equivalent to the fourth 64-bit data element added to a value equivalent to the second 64-bit result element rotated right by nineteen bits XOR'd with the second 64-bit result element rotated right by sixty-one bits XOR'd with the second 64-bit result element shifted right by six bits; and
storing the result in a destination.
20. The non-transitory machine readable storage medium of claim 19 , wherein the first 64-bit data element is to be stored in bits [63:0] of the first vector register, the second 64-bit data element is to be stored in bits [127:64] of the first vector register, the third 64-bit data element is to be stored in bits [191:128] of the first vector register, and the fourth 64-bit data element is to be stored in bits [255:192] of the first vector register, and wherein the first instruction specifies a YMM register.