Method and apparatus for dual multiplication units in a data path

1. A system comprising:

a first multiplication unit;

a second multiplication unit;

a first data path including the first multiplication unit and the second multiplication unit; and

an instruction dispatch unit coupled to the first data path and configured to;

receive a first instruction including a first instruction type field indicating a dual issue instruction type;

dispatch the first instruction to the first multiplication unit and to the second multiplication unit in response to the first instruction type field indicating the dual issue instruction type;

receive a second instruction including a second instruction type field indicating a single issue instruction type; and

dispatch the second instruction to the first multiplication unit and not to the second multiplication unit in response to the second instruction t field indicating the single issue instruction type,

wherein the first multiplication unit and the second multiplication unit are configured to execute the first instruction to generate a first result, and

wherein the first multiplication unit is configured to execute the second instruction to generate a second result.

2. The system of claim 1 , further comprising:

a third multiplication unit;

a fourth multiplication unit; and

a second data path including the third multiplication unit and the fourth multiplication unit;

wherein the third multiplication unit is configured to execute a third instruction.

3. The system of claim 2 , wherein the third instruction includes a third instruction type field indicating one of the single issue instruction type and the dual issue instruction type.

4. The system of claim 2 , wherein the first data path is a scalar data path and the second data path is a vector data path.

5. The system of claim 1 , further comprising a processor configured to withhold issuing subsequent instructions to the second multiplication unit until the first instruction is completed.

6. The system of claim 1 , wherein:

the first multiplication unit includes a first number of multipliers;

a subset of the first number of multipliers executes the first instruction to generate the first result;

the first result includes a set of most significant bits and a set of least significant bits;

the set of least significant bits are communicated by the first multiplication unit;

the set of the most significant bits are communicated by the second multiplication unit.

7. The system of claim 1 , wherein the first instruction includes:

a destination field indicating a destination register for the first result;

a source field; and

an opcode field encoding a functional unit associated with the first instruction.

8. The system of claim 7 , wherein:

the destination field indicates a single register; and

a write to the single register is by the first multiplication unit.

9. The system of claim 7 , wherein:

the destination field indicates a register pair including a first register and a second register;

the first multiplication unit writes to the first register; and

the second multiplication unit writes to the second register.

10. The system of claim 7 , wherein:

the source field indicates a single register; and

a read to the single register is by the first multiplication unit and the second multiplication unit.

11. The system of claim 7 , wherein:

the source field indicates a register pair including a first register and a second register;

the first multiplication unit reads from the first register; and

the second multiplication unit reads from the second register.

12. A method comprising:

decoding, by a processor, a first instruction including a first instruction type field indicating a dual issue instruction type;

dispatching the first instruction to a first multiplication unit and to a second multiplication unit in response to the first instruction type field indicating the dual issue instruction type;

executing the first instruction by the first multiplication unit and the second multiplication unit in a first data path of the processor;

storing, by the processor, a first result of the first instruction in a first storage location indicated by the first instruction;

decoding, by the processor, a second instruction including a second instruction type field indicating a single issue instruction type;

dispatching the second instruction to the first multiplication unit and not to the second multiplication unit in response to the second instruction type field indicating the single issue instruction type;

executing the second instruction by the first multiplication unit; and

storing, by the processor, a second result of the second instruction in a second storage location indicated by the second instruction.

13. The method of claim 12 , further comprising:

decoding, by the processor, a third instruction having a third instruction type field indicating the single issue instruction type;

dispatching the third instruction to a third multiplication unit and not to the first multiplication unit or the second multiplication unit in response to the third instruction type field indicating the single issue instruction type;

executing the third instruction by the third multiplication unit in a second data path of the processor; and

storing, by the processor, a third result of the third instruction in a third storage location indicated by the third instruction.

14. The method of claim 13 , wherein:

the first data path is a scalar data path and the second data path is a vector data path; and

the processor is configured to withhold issuing subsequent instructions to the second multiplication unit until the first instruction is completed.

15. The method of claim 13 , wherein:

the first instruction includes:

a first destination field indicating a first destination register for the first result;

a first source field; and

a first opcode field encoding a first functional unit associated with the first instruction, wherein the first functional unit includes the first multiplication unit and the second multiplication unit; and

the second instruction includes:

a second destination field indicating a second destination register for the second result;

a second source field; and

a second opcode field encoding a second functional unit associated with the second instruction,

wherein the second functional unit includes the first multiplication unit and not the second multiplication unit.

16. The method of claim 15 , wherein:

the first destination field indicates a single register; and

a write to the single register is by the first multiplication unit.

17. The method of claim 15 , wherein:

the first destination field indicates a register pair including a first register and a second register;

the first multiplication unit writes to the first register; and

the second multiplication unit writes to the second register.

18. The method of claim 15 , wherein:

the first source field indicates a single register; and

a read to the single register is by the first multiplication unit and the second multiplication unit.

19. The method of claim 15 , wherein:

the first source field indicates a register pair including a first register and a second register;

the first multiplication unit reads from the first register; and

the second multiplication unit reads from the second register.

20. The method of claim 12 , wherein:

the first multiplication unit includes a first number of multipliers;

a subset of the first number of multipliers executes the first instruction to generate the first result;

the first result includes a set of most significant bits and a set of least significant bits;

the set of least significant bits are communicated by the first multiplication unit;

the set of the most significant bits are communicated by the second multiplication unit.