Nanopore transistor for biosensing
A method for forming a nanopore transistor and a nanopore transistor is provided. The method includes: (a) forming an aperture in a filler material by: (i) providing a fin comprising a semiconductor layer and a top layer; (ii) patterning the top layer to form a pillar; (iii) embedding the pillar in a filler material; (iv) removing the pillar, leaving an aperture; (v) lining the aperture with a spacer material; (b) forming a nanopore by etching through the aperture; (b) lining the nanopore with a dielectric, (c) forming a source and a drain by either: between steps a.ii and a.iii, doping the bottom semiconductor layer by using the pillar as a mask, or after step c, filling the aperture with a sealing material, thereby forming a post; removing the filler material; doping the bottom semiconductor layer by using the post as a mask; and removing the sealing material.
1. A method for forming a nanopore transistor for biosensing, the method comprising:
(a) forming an aperture in a filler material by:
(i) providing a fin structure comprising at least a bottom semiconductor layer and a top layer;
(ii) patterning the top layer to form a pillar;
(iii) laterally embedding the pillar in the filler material;
(iv) forming the aperture in the filler material by removing the pillar;
(v) lining the aperture with a spacer material, thereby reducing a size of the aperture;
(b) forming a nanopore in the bottom semiconductor layer by etching through the aperture;
(c) lining the nanopore with a gate dielectric material, thereby forming a gate dielectric; and
(d) forming a source and a drain by either:
(i) between steps a.ii and a.iii, doping the bottom semiconductor layer by ion implantation using the pillar as a mask, or
(ii) after step b,
filling the aperture with a sealing material so that the sealing material is coplanar with the filler material, thereby forming a post comprising the sealing material and the spacer material;
removing the filler material selectively with respect to the post, thereby exposing a part of the bottom semiconductor layer;
doping the bottom semiconductor layer by ion implantation by using the post as a mask; and
removing the sealing material.
2. The method of claim 1 , wherein the step a.ii comprises self-aligning the pillar on the bottom semiconductor layer using a line mask intersecting the fin structure.
3. The method of claim 1 , wherein the filler material is silicon dioxide.
4. The method of claim 1 , wherein the spacer material is selected from the group consisting of: silicon dioxide; silicon nitride, silicon oxycarbide, and a metal.
5. The method of claim 1 , wherein the bottom semiconductor layer comprises silicon.
6. The method of claim 1 , wherein the top layer comprises a first mask material and a second mask material, different from the first mask material, and arranged on top of the first mask material, wherein the first mask material is an etch stop material protecting the bottom semiconductor layer during etching of the second mask material.
7. The method of claim 6 , wherein the first mask material is selected from the group consisting of: silicon dioxide, silicon nitride, silicon oxycarbide, and silicon oxynitride, and wherein the second mask material is selected from the group consisting of: amorphous silicon, titanium nitride, silicon dioxide, silicon nitride, silicon oxycarbide, and silicon oxynitride.
8. The method of claim 1 , wherein the gate dielectric material is an oxide.
9. The method of claim 1 , further comprising a step c′ performed:
between steps a.ii and d if step d.i is performed, comprising forming spacers around the pillar, and comprising using the pillar and the spacers as a mask during step d.i, or
during step d.ii, between the step of removing the filler material and the doping step, comprising forming spacers around the post, and comprising using the post and the spacers as a mask during the doping step.
10. The method of claim 1 , wherein step b is performed after step a.v and before step d and wherein the sealing material is the same as the spacer material.
11. The method according to claim 10 , wherein both the sealing material and the spacer material is silicon nitride.
12. The method of claim 1 , wherein in step d.ii, the step of filling the aperture with the sealing material comprises overfilling the aperture with the sealing material so that the sealing material covers part of the filler material, followed by removing a top portion of the sealing material until it no longer covers the filler material.
13. The method of claim 1 , further comprising a step d′, after step d, of exposing the bottom semiconductor layer to heat so as to activate dopants introduced in step d.
14. The method of claim 1 , wherein a width of the nanopore ranges from 1 to 34 nm.
15. The method of claim 1 , wherein a width of the nanopore region ranges from 1 to 20 nm.
16. The method of claim 1 , wherein a width of the nanopore region ranges from 5 to 15 nm.