Semiconductor device with backside spacer and methods of forming the same

1. A method of forming a semiconductor device, comprising:

epitaxially growing a sacrificial layer over a substrate;

epitaxially growing a bottom semiconductor layer over the sacrificial layer;

forming a semiconductor stack over the bottom semiconductor layer, wherein the semiconductor stack includes first semiconductor layers and second semiconductor layers interleaving the first semiconductor layers;

forming dummy gate structures over the semiconductor stack;

forming a source/drain (S/D) trench between two adjacent dummy gate structures of the dummy gate structures, wherein the S/D trench extends partially into the substrate;

epitaxially growing a semiconductor feature in the S/D trench,

epitaxially growing a S/D feature over the semiconductor feature in the S/D trench;

removing the substrate and replacing the sacrificial layer with a dielectric layer;

removing the semiconductor feature to form a backside trench, wherein the backside trench includes a main portion along sidewalls of the dielectric layer and extending to a bottom surface of the S/D feature and a side portion laterally away from the main portion and along a sidewall of the bottom semiconductor layer;

forming a backside spacer in the side portion of the backside trench; and

forming a conductive feature in the main portion of the backside trench.

2. The method of claim 1 , wherein a composition of the bottom semiconductor layer is different from a composition of the sacrificial layer.

3. The method of claim 2 ,

wherein the bottom semiconductor layer comprises silicon,

wherein the sacrificial layer comprises silicon germanium.

4. The method of claim 1 , wherein the removing the semiconductor feature an isotropic etching process.

5. The method of claim 1 , wherein the backside spacer includes a dielectric material different from a material of the dielectric layer.

6. The method of claim 1 , wherein a width of the side portion of the backside trench is about 20% to about 25% of a width of the main portion of the backside trench.

7. The method of claim 1 , wherein the forming the conductive feature in the main portion of the backside trench includes:

pre-cleaning the backside trench to laterally remove a side portion of the dielectric layer such that an opening of the backside trench is enlarged; and

forming the conductive feature in the backside trench.

8. The method of claim 7 , wherein the opening of the backside trench is enlarged for about 25% to about 45%.

9. The method of claim 7 , further comprising:

forming inner spacers between side portions of the first semiconductor layers;

removing the dummy gate structures and the second semiconductor layers to form gate trenches;

forming metal gate structures in the gate trenches; and

forming a silicide layer between the conductive feature and the S/D feature, wherein the silicide layer laterally contacts the inner spacers.

10. A method, comprising:

epitaxially growing a silicon germanium layer over a substrate;

epitaxially growing a bottom silicon layer over the silicon germanium layer;

forming a semiconductor stack over the bottom silicon layer, wherein the semiconductor stack includes first semiconductor layers interleaved by second semiconductor layers;

patterning the semiconductor stack to form a fin-shaped structure;

forming a first dummy gate structure and a second dummy gate structure over the fin-shaped structure;

forming a source/drain (S/D) trench between the first dummy gate structure and the second dummy gate structure, wherein the S/D trench extends partially into the substrate;

forming a plurality of inner spacer features to interleave the first semiconductor layers

depositing a semiconductor feature in the S/D trench;

epitaxially growing a S/D feature over the semiconductor feature in the S/D trench;

removing the substrate;

replacing the silicon germanium layer with a bottom dielectric layer;

removing the semiconductor feature to expose the S/D feature in a backside trench, wherein the backside trench extends laterally to undercut a bottommost inner spacer feature of the plurality of inner spacer features;

forming a backside spacer below the bottommost inner spacer feature and adjacent the bottom silicon layer; and

forming a conductive feature in the backside trench.

11. The method of claim 10 , wherein the substrate comprises a first silicon layer, a second silicon layer disposed over the first silicon layer, and a silicon oxide layer sandwiched between the first silicon layer and the second silicon layer.

12. The method of claim 10 , further comprising:

before the epitaxially growing of the S/D feature, depositing an undoped silicon layer on the semiconductor feature.

13. The method of claim 10 , wherein the removing of the semiconductor feature comprises:

performing an anisotropic selective etch; and

performing an isotropic selective etch.

14. The method of claim 13 , wherein the isotropic selective etch comprises use of potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), other alkaline solution, or a combination thereof.

15. The method of claim 13 , wherein the isotropic selective etch comprises ammonium hydroxide (NH 4 OH).

16. The method of claim 15 , wherein the isotropic selective etch comprises a temperature between about 50° C. and about 70° C.

17. The method of claim 10 , further comprising:

before the removing of the substrate, removing the first dummy gate structure and the second dummy gate structure;

selectively removing the second semiconductor layers to release the first semiconductor layers as channel semiconductor layers; and

forming a gate structure to wrap around each of the channel semiconductor layers.

18. A method, comprising:

receiving a workpiece comprising:

a substrate,

a sacrificial layer over the substrate,

a bottom semiconductor layer over the sacrificial layer,

a first stack of channel nanostructures and a second stack of channel nanostructures over the bottom semiconductor layer,

a first plurality of inner spacer features interleaving the first stack of channel nanostructures,

a second plurality of inner spacer features interleaving the second stack of channel nanostructures,

a source/drain (S/D) feature extending between the first stack of channel nanostructures and the second stack of channel nanostructures, and

a semiconductor feature disposed below the S/D feature and extending through the bottom semiconductor layer and the sacrificial layer;

removing the substrate to expose the sacrificial layer and the semiconductor feature;

replacing the sacrificial layer with a bottom dielectric layer;

removing the semiconductor feature to expose the S/D feature in a backside trench, wherein the backside trench includes a main portion along sidewalls of the bottom dielectric layer and extending to a bottom surface of the S/D feature and a side portion laterally away from the main portion and along a sidewall of the bottom semiconductor layer;

forming a backside spacer in the side portion of the backside trench; and

forming a conductive feature in the main portion of the backside trench.

19. The method of claim 18 , wherein the workpiece further an undoped silicon layer sandwiched between the semiconductor feature and the S/D feature.

20. The method of claim 18 , wherein the semiconductor feature comprises:

performing an anisotropic selective etch; and

performing a selective dry etching using ammonium hydroxide (NH4OH) at a temperature of about 50° C. to about 70° C.