Semiconductor package including redistribution pattern
A semiconductor package includes a semiconductor chip including a connecting pad, a mold layer covering the semiconductor chip, a lower redistribution layer on the semiconductor chip and the mold layer, and a connecting terminal on the lower redistribution layer. The lower redistribution layer includes a first lower insulating layer, a first conformal redistribution pattern extending through the first lower insulating layer, a second lower insulating layer on the first lower insulating layer and the first conformal redistribution pattern, and a first filled redistribution pattern disposed on the first conformal redistribution pattern and extending through the second lower insulating layer. A side surface of the first filled redistribution pattern is spaced apart from an inner side surface of the first conformal redistribution pattern. The second lower insulating layer is between the inner side surface of the first conformal redistribution pattern and the side surface of the first filled redistribution pattern.
1. A semiconductor package comprising:
a semiconductor chip comprising a connecting pad;
a mold layer covering the semiconductor chip;
a lower redistribution layer on the semiconductor chip and the mold layer; and
a connecting terminal on the lower redistribution layer,
wherein the lower redistribution layer comprises
a first lower insulating layer,
a first conformal redistribution pattern extending through the first lower insulating layer, the first conformal redistribution pattern including a top horizontal portion, a bottom horizontal portion, and a connecting portion interconnecting the top horizontal portion and the bottom horizontal portion,
a second lower insulating layer on the first lower insulating layer and the first conformal redistribution pattern, and
a first filled redistribution pattern on the first conformal redistribution pattern, the first filled redistribution pattern extending through the second lower insulating layer, the first filled redistribution pattern including a via and a conductive pattern, the via being a filled pattern extending through the second lower insulating layer, an entirety of a top surface of the via being in contact with the conductive pattern, the conductive pattern extending horizontally on the second lower insulating layer,
wherein a side surface of the first filled redistribution pattern is spaced apart from an inner side surface of the connecting portion of the first conformal redistribution pattern, and
wherein the second lower insulating layer is between the inner side surface of the first conformal redistribution pattern and the side surface of the first filled redistribution pattern.
2. The semiconductor package according to claim 1 , wherein:
the first conformal redistribution pattern comprises a first via and a first conductive pattern;
the first via comprises a top surface and a side surface that define a recess; and
the second lower insulating layer contacts the top surface of the first via and filling the recess of the first via.
3. The semiconductor package according to claim 2 , wherein the second lower insulating layer completely covers the side surface of the first via.
4. The semiconductor package according to claim 2 , wherein:
the first filled redistribution pattern comprises a second via and a second conductive pattern; and
a side surface of the second via is spaced apart from the side surface of the first via.
5. The semiconductor package according to claim 4 , wherein the second lower insulating layer completely surrounds the side surface of the second via.
6. The semiconductor package according to claim 2 , wherein:
the connecting pad comprises a first top surface, a second top surface, and a side surface interconnecting the first top surface and the second top surface; and
the first conformal redistribution pattern completely covers the first top surface and the side surface of the connecting pad.
7. The semiconductor package according to claim 6 , wherein a minimum distance between the second top surface of the connecting pad and a bottom surface of the first conductive pattern is about 3 to 10 μm.
8. The semiconductor package according to claim 1 , further comprising:
a third lower insulating layer on the second lower insulating layer; and
a second conformal redistribution pattern being on the first filled redistribution pattern and extending through the third lower insulating layer.
9. The semiconductor package according to claim 1 , further comprising:
a third lower insulating layer on the second lower insulating layer;
a second filled redistribution pattern being on the first filled redistribution pattern and extending through the third lower insulating layer; and
a second conformal redistribution pattern being on the second filled redistribution pattern.
10. The semiconductor package according to claim 8 , further comprising:
a fourth lower insulating layer being on the second conformal redistribution pattern and filling a recess of the second conformal redistribution pattern.
11. The semiconductor package according to claim 10 , further comprising:
a second filled redistribution pattern being on the second conformal redistribution pattern and extending through the fourth lower insulating layer.
12. The semiconductor package according to claim 11 , wherein:
the second conformal redistribution pattern comprises a first via and a first conductive pattern;
the first via comprises a top surface and a side surface that define a recess; and
the fourth lower insulating layer contacts the top surface of the first via and fills the recess of the first via.
13. The semiconductor package according to claim 12 , wherein:
the second filled redistribution pattern comprises a second via and a second conductive pattern; and
a side surface of the second via is spaced apart from the side surface of the first via.
14. The semiconductor package according to claim 13 , wherein the fourth lower insulating layer is between the side surface of the first via and the side surface of the second via.
15. The semiconductor package according to claim 13 , wherein the fourth lower insulating layer completely surrounds the side surface of the second via.
16. A semiconductor package comprising:
a base layer comprising an opening;
a conductive connector extending through the base layer;
a semiconductor chip in the opening;
a mold layer covering a top surface of each of the base layer and the semiconductor chip; and
a lower redistribution layer on the base layer, the semiconductor chip and the mold layer,
wherein the semiconductor chip comprises a die, a chip pad on the die, and a connecting pad on the chip pad, the connecting pad comprising a first horizontal top surface, a second horizontal top surface, and an inner side surface interconnecting the first horizontal top surface and the second horizontal top surface,
wherein the lower redistribution layer comprises
a first lower insulating layer on the semiconductor chip,
a first lower redistribution pattern extending through the first lower insulating layer, the first lower redistribution pattern comprising a first via and a first conductive pattern, the first via extending through the first lower insulating layer and being in contact with the first horizontal top surface of the connecting pad, and the first conductive pattern being on the first via and extending horizontally on the first lower insulating layer, and
a second lower redistribution pattern on the first lower redistribution pattern,
wherein a side surface of the first via is spaced apart from the inner side surface of the connecting pad, and
wherein the first lower insulating layer is between the side surface of the first via and the inner side surface of the connecting pad.
17. The semiconductor package according to claim 16 , wherein the first lower insulating layer contacts a portion of the first horizontal top surface of the connecting pad and the inner side surface of the connecting pad.
18. The semiconductor package according to claim 16 , wherein the first lower insulating layer completely surrounds the side surface of the first via.
19. The semiconductor package according to claim 16 , wherein the second lower redistribution pattern is a conformal redistribution pattern or a filled redistribution pattern.
20. A semiconductor package comprising:
a semiconductor chip comprising a chip pad;
a mold layer covering the semiconductor chip;
a lower redistribution layer on a bottom surface of the mold layer; and
a conductive connector connected to the lower redistribution layer and extending through the mold layer,
wherein the lower redistribution layer comprises,
an under bump metal (UBM),
a first lower insulating layer covering the UBM,
a first conformal redistribution pattern on the UBM, the first conformal redistribution pattern extending through the first lower insulating layer, the first conformal redistribution pattern including a top horizontal portion, a bottom horizontal portion, and a connecting portion interconnecting the top horizontal portion and the bottom horizontal portion,
a second lower insulating layer on the first conformal redistribution pattern; and
a first filled redistribution pattern on the first conformal redistribution pattern, the first filled redistribution pattern extending through the second lower insulating layer, the first filled redistribution pattern including a via and a conductive pattern, the via being a filled pattern extending through the second lower insulating layer, an entirety of a top surface of the via being in contact with the conductive pattern, the conductive pattern extending horizontally on the second lower insulating layer,
wherein a side surface of the first filled redistribution pattern is spaced apart from an inner side surface of the connecting portion of the first conformal redistribution pattern, and
wherein the second lower insulating layer is between the inner side surface of the first conformal redistribution pattern and the side surface of the first filled redistribution pattern.